- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370005 > PLL1706 RS232/EIA562/RS485 Transceivers; Package: PDIP; No of Pins: 24; Temperature Range: -40°C to +85°C PDF資料下載
參數(shù)資料
| 型號： | PLL1706 |
| 英文描述： | RS232/EIA562/RS485 Transceivers; Package: PDIP; No of Pins: 24; Temperature Range: -40°C to +85°C |
| 中文描述： | 3.3伏雙PLL的多時鐘發(fā)生器 |
| 文件頁數(shù)： | 12/17頁 |
| 文件大?。?/td> | 128K |
| 代理商： | PLL1706 |
PLL1705
PLL1706
SLES046A
–
AUGUST 2002
–
REVISED SEPTEMBER 2002
www.ti.com
12
Program-Register Bit Mapping
The built-in functions of the PLL1706 are controlled through a 16-bit program register. This register is loaded using MD,
MC and ML. After the 16 data bits are clocked in using the rising edge of MC, ML is used to latch the data into the register.
Table 6 shows the bit mapping of the register. The serial mode control format and control data input timing are shown in
Figure 12 and Figure 13, respectively.
ML
MC
MD
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 12. Serial Mode Control Format
t(MLL)
VDD/2
MC
MD
MSB
ML
t(MHH)
VDD/2
VDD/2
t(MLS)
t(MLH)
t(MCL)
t(MCH)
LSB
t(MDH)
t(MCY)
t(MDS)
t(MLS)
DESCRIPTION
SYMBOL
tMCY
tMCL
tMCH
tMDH
tMDS
tMLL
tMHH
tMLH
tMLS
MIN
100
40
40
40
40
16
200
40
40
TYP
MAX
UNIT
ns
ns
ns
ns
ns
MC pulse cycle time
MC pulse duration LOW
MC pulse duration HIGH
MD hold time
MD setup time
ML low-level time
ML high-level time
ML hold time(2)
ML setup time(3)
(1)MC clocks: MC clock period
(2)MC rising edge for LSB to ML rising edge
(3)ML rising edge to the next MC rising edge. If the MC clock is stopped after the LSB, any ML rise time is accepted.
MC clocks(1)
ns
ns
ns
Figure 13. Control Data Input Timing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PLL1810A | RS232/EIA562/RS485 Transceivers; Package: PDIP; No of Pins: 24; Temperature Range: -40°C to +85°C |
| PLL2001P | Serial-Input Frequency Synthesizer |
| PLL2013X | PLL2013X 20MHZ~170MHZ FSPLL PLL2013X|Data Sheet |
| PLL2014X | 8-Channel Analog Multiplexer with Cascadable Serial Interface; Package: SSOP; No of Pins: 16; Temperature Range: 0°C to +70°C |
| PLL2026X | 8-Channel Analog Multiplexer with Cascadable Serial Interface; Package: PDIP; No of Pins: 16; Temperature Range: 0°C to +70°C |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PLL1706DBQ | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3.3 V Dual PLL Multi Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PLL1706DBQG4 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3.3V Dual PLL Multi- Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PLL1706DBQR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3.3V Dual PLL Multi- Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PLL1706DBQRG4 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3.3V Dual PLL Multi- Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PLL1707 | 制造商:BB 制造商全稱:BB 功能描述:3.3 V DUAL PLL MULTICLOCK GENERATOR |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。