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參數資料
| 型號： | PLL2108X |
| 英文描述： | PLL2108X 50MHz ~ 300MHz FSPLL|Data Sheet |
| 中文描述： | PLL2108X高達50MHz?300MHz的FSPLL |數據資料 |
| 文件頁數： | 7/10頁 |
| 文件大?。?/td> | 150K |
| 代理商： | PLL2108X |
SEC ASIC
50MHz~300MHz FSPLL
ANALOG
PLL2108X
CORE LAYOUT GUIDE
1. The digital power(AVDD12D,AVSS12D) and the analog power(AVDD12A, AVSS12A) must be dedicated
to PLL only and separated. If the dedicated AVDD12D and AVSS12D are not allowed, please consult with
SEC application engineer.
2. The FOUT and FILTER pins must be placed far from the internal signals in order to avoid cross-talk
between the signal lines.
3. The blocks showing a large amount of digital switching current must be located away from the PLL core.
DESIGN CONSIDERATIONS
The following design considerations must be applied:.
1. Jitter is affected by the power noise, substrate noise, etc. It goes up when the noise level increases.
2. A CMOS-level input reference clock is recommend for signal compatibility with the PLL circuit. Other
levels such as TTL may degrade the tolerances.
3. The use of two, or more PLLs requires special design considerations. Please consult with SEC application
engineer for more information.
4. The PLL core should be placed as close as possible to the dedicated loop filter and analog power and
ground pins.
5. It is inadvisable to locate noise-generating signals near the PLL and its I/O cells.
high frequency outputs and high current consuming cells, .
6. Other related I/O signals should be placed near the PLL I/O but do not have any pre-defined placement
restriction
For example, data buses,
7/10
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