參數(shù)資料
型號(hào): PLL2127X
英文描述: PLL2127X 20MHz ~ 100MHz FSPLL|Data Sheet
中文描述: PLL2127X為20MHz?100MHz的FSPLL |數(shù)據(jù)資料
文件頁(yè)數(shù): 6/10頁(yè)
文件大?。?/td> 150K
代理商: PLL2127X
SEC ASIC
50MHz~300MHz FSPLL
ANALOG
PLL2108X
CORE EVALUATION GUIDE
1.You can generate various output frequencies by changing M/P/S setting. There are two methods of controlling
divider values
-
Method 1: 16 bit register can be used for easy control of divider values.
-
Method 2: P, M and S pins are bypassed to the external port, and you can control each port directly.
It is undesirable to connect P[5:0], M[7:0] and S[1:0] to the internal power or ground directly
6/10
NOTES
: 10uF ELECTROLYTIC CAPACITOR
UNLESS OTHERWISE SPECIFIED
: 0.1uF CERAMIC CAPACITOR
UNLESS OTHERWISE SPECIFIED
FIN
PWRDN
P[5:0]
M[7:0]
S[1:0]
FOUT
AVDD12A
AVSS12A
VABB
AVDD12D
AVSS12D
VABB
FILTER
1.8 nF (Chip cap)
1.2V
GND
pll2108x
S1
M7
M6
M5
M4
M3
M2
M1
M0
P0
P1
P2
P3
P4
P5
S0
1
1
1
1
相關(guān)PDF資料
PDF描述
PLL2128X PLL2128X 20MHz ~ 100MHz FSPLL|Data Sheet
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PLL2128X 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PLL2128X 20MHz ~ 100MHz FSPLL|Data Sheet
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