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參數(shù)資料
| 型號(hào)： | PLSI1016E100LT44I |
| 廠(chǎng)商： | Lattice Semiconductor Corporation |
| 英文描述： | High-Density Programmable Logic |
| 中文描述： | 高密度可編程邏輯 |
| 文件頁(yè)數(shù)： | 8/15頁(yè) |
| 文件大?。?/td> | 208K |
| 代理商： | PLSI1016E100LT44I |
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8
1996 ISP Encyclopedia
Specifications
ispLSI and pLSI 1016E
ispLSI and pLSI 1016E Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
Reg 4 PT Bypass
#35
20 PT
XOR Delays
Control
PTs
#44-46
Input
RST
DiClock
I/O Pin
(Input)
Y0
Y1,2
D
Q
GLB Reg Bypass
#39
ORP Bypass
#48
D
Q
RST
RE
OE
CK
I/O Reg Bypass
#22
I/O Cell
ORP
GLB
GRP
I/O Cell
#23 - 27
#30
LDelay
#36-38
#55-58
#54
#47
Reset
Ded. In
GOE 0
#28
#59
#59
#40-43
#51, 52
0491-16
Comb 4 PT Bypass #34
#53
#29, 31, 32
#49, 50
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
1
=
=
=
=
(0.3 + 1.9 + 4.4) + (0.2) - (0.3 + 1.9 + 3.2)
1.4 ns
t
su
Logic + Reg su - Clock (min)
(
t
iobp +
t
grp4 +
t
20ptxor) + (
t
gsu) - (
t
iobp +
t
grp4 +
t
ptck(min))
(#22 + #30 + #37) + (#40) - (#22 + #30 + #46)
=
=
=
=
t
h
Clock (max) + Reg h - Logic
(
t
iobp +
t
grp4 +
t
ptck(max)) + (
t
gh) - (
t
iobp +
t
grp4 +
t
20ptxor)
(#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
(0.3 + 1.9 + 3.5) + (1.5) - (0.3 + 1.9 + 4.4)
0.6 ns
=
=
=
=
t
co
Clock (max) + Reg co + Output
(
t
iobp +
t
grp4 +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#22 + #30 + #46) + (#42) + (#47 + #49)
(0.3 + 1.9 + 3.5) + (1.8) + (1.0 + 1.4)
9.9 ns
Table 2-0042-16
Derivations of
t
su,
t
h and
t
co from the Clock GLB
1
=
=
=
=
(0.3 + 1.9 + 4.4) + (0.2) - (1.3 + 1.8 + 0.8)
2.9 ns
t
su
Logic + Reg su - Clock (min)
(
t
iobp +
t
grp4 +
t
20ptxor) + (
t
gsu) - (
t
gy0(min) +
t
gco +
t
gcp(min))
(#22 + #30 + #37) + (#40) - (#54 + #42 + #56)
=
=
=
=
t
h
Clock (max) + Reg h - Logic
(
t
gy0(max) +
t
gco +
t
gcp(max)) + (
t
gh) - (
t
iobp +
t
grp4 +
t
20ptxor)
(#54 + #42 + #56) + (#41) - (#22 + #30 + #37)
(1.3 + 1.8 + 1.8) + (1.5) - (0.3 + 1.9 + 4.4)
-0.2 ns
=
=
=
=
t
co
Clock (max) + Reg co + Output
(
t
gy0(max) +
t
gco +
t
gcp(max)) + (
t
gco) + (
t
orp +
t
ob)
(#54 + #42 + #56) + (#42) + (#47 + #49)
(1.3 + 1.8 + 1.8) + (1.8) + (1.0 + 1.4)
9.1 ns
1. Calculations are based upon timing specifications for the ispLSI and pLSI 1016E-
125
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| PLSI1016E125LJ | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:High-Density Programmable Logic |
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| PLSI1016E125LT44I | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:High-Density Programmable Logic |
| PLSI1016E80LJ | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:High-Density Programmable Logic |
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