參數(shù)資料
型號: PLSI1016E80LJ
廠商: Lattice Semiconductor Corporation
英文描述: High-Density Programmable Logic
中文描述: 高密度可編程邏輯
文件頁數(shù): 5/15頁
文件大?。?/td> 208K
代理商: PLSI1016E80LJ
5
1996 ISP Encyclopedia
Specifications
ispLSI and pLSI 1016E
External Timing Parameters
Over Recommended Operating Conditions
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
UNITS
-125
MIN.
125
TEST
COND.
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions Section.
Table 2-0030-16/125,100, 80
1
4
3
1
( )
-100
MIN.
100
MAX.
7.5
10.0
MAX.
10.0
13.0
DESCRIPTION
#
2
PARAMETER
A
A
A
1
2
3
Data Prop. Delay, 4PT Bypass, ORP Bypass
Data Prop. Delay, Worst Case Path
Clk. Frequency with Int. Feedback
ns
ns
MHz
A
4
5
6
7
8
Clk. Frequency with Ext. Feedback
Clk. Frequency, Max. Toggle
GLB Reg. Setup Time before Clk., 4 PT Bypass
GLB Reg. Clk. to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clk., 4 PT Bypass
MHz
MHz
ns
ns
ns
0.0
A
B
C
B
C
9
GLB Reg. Setup Time before Clk.
10 GLB Reg. Clk. to Output Delay
11 GLB Reg. Hold Time after Clk.
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
5.5
0.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
wh
t
wl
t
su3
t
h3
18 Ext. Sync. Clk. Pulse Duration, High
19 Ext. Sync. Clk. Pulse Duration, Low
3.0
3.0
4.0
4.0
ns
ns
20 I/O Reg. Setup Time before Ext. Sync. Clk. (Y2, Y3) 3.0
21 I/O Reg. Hold Time after Ext. Sync. Clk. (Y2, Y3)
ns
ns
0.0
100
167
5.0
4.5
5.5
10.0
12.0
12.0
7.0
7.0
77
125
7.0
0.0
8.0
0.0
6.5
3.5
0.0
5.0
6.0
13.5
15.0
15.0
9.0
9.0
( )
1
-80
MIN. MAX.
15.0
18.5
84.0
57.0
100
8.5
8.0
0.0
9.5
9.5
0.0
17.0
10.0
20.0
20.0
10.5
10.5
5.0
5.0
0.0
4.5
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