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參數(shù)資料
| 型號： | PLSI1032-90LJ |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | High-Density Programmable Logic |
| 中文描述： | EE PLD, 17 ns, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 1/19頁 |
| 文件大?。?/td> | 256K |
| 代理商： | PLSI1032-90LJ |
Specifications
ispLSI and pLSI 1032
ispLSI
High-Density Programmable Logic
1
1996 ISP Encyclopedia
1032_02
Functional Block Diagram
Output Routing Pool
Output Routing Pool
D7 D6 D5 D4 D3 D2 D1 D0
B0 B1 B2 B3 B4 B5 B6 B7
A0
A1
A2
A3
A4
A5
A6
A7
C7
C6
C5
C4
C3
C2
C1
C0
O
CLK
O
Global Routing Pool (GRP)
Logic
Array
D Q
D Q
D Q
D Q
GLB
Description
The ispLSI and pLSI 1032 are High-Density Program-
mable Logic Devices containing 192 Registers, 64
Universal I/O pins, eight Dedicated Input pins, four Dedi-
cated Clock Input pins and a Global Routing Pool (GRP).
The GRP provides complete interconnectivity between
all of these elements. The ispLSI 1032 features 5-Volt in-
system programming and in-system diagnostic
capabilities. It is the first device which offers non-volatile
"on-the-fly" reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems. It is
architecturally and parametrically compatible to the pLSI
1032 device, but multiplexes four of the dedicated input
pins to control in-system programming.
The basic unit of logic on the ispLSI and pLSI 1032
devices is the Generic Logic Block (GLB). The GLBs are
labeled A0, A1 .. D7 (see figure 1). There are a total of
32 GLBs in the ispLSI and pLSI 1032 devices. Each GLB
has 18 inputs, a programmable AND/OR/XOR array, and
four outputs which can be configured to be either combi-
natorial or registered. Inputs to the GLB come from the
GRP and dedicated inputs. All of the GLB outputs are
brought back into the GRP so that they can be connected
to the inputs of any other GLB on the device.
Features
HIGH-DENSITY PROGRAMMABLE LOGIC
— High Speed Global Interconnect
— 6000 PLD Gates
— 64 I/O Pins, Eight Dedicated Inputs
— 192 Registers
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Fast Random Logic
— Security Cell Prevents Unauthorized Copying
HIGH PERFORMANCE E
2
CMOS
TECHNOLOGY
—
f
max
= 90 MHz Maximum Operating Frequency
—
f
max
= 60 MHz for Industrial and Military/883 Devices
—
t
pd
= 12 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E
2
CMOS Technology
— 100% Tested
ispLSI OFFERS THE FOLLOWING ADDED FEATURES
— In-System Programmable (ISP) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
ispLSI AND pLSI DEVELOPMENT TOOLS
pDS
Software
— Easy to Use PC Windows Interface
— Boolean Logic Compiler
— Manual Partitioning
— Automatic Place and Route
— Static Timing Table
ispDS+ Software
— Industry Standard, Third Party Design
Environments
— Schematic Capture, State Machine, HDL
— Automatic Partitioning and Place and Route
— Comprehensive Logic and Timing Simulation
— PC and Workstation Platforms
and pLSI
1032
Copyright 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com
February 1997
1996 ISP Encyclopedia
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PLSI1032-90LT | Circular Connector; Body Material:Aluminum Alloy; Series:KPSE06; No. of Contacts:15; Connector Shell Size:14; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Circular Contact Gender:Socket; Insert Arrangement:14-15 RoHS Compliant: No |
| PLT06381 | LIGHT-DEPENDENT-RESISTOR-OUTPUT OPTOCOUPLER |
| PLT06681 | LIGHT-DEPENDENT-RESISTOR-OUTPUT OPTOCOUPLER |
| PLT12381 | Micropower, Regulated 3.3V/5V Charge Pump with Shutdown in SOT-23; Package: SOT; No of Pins: 6; Temperature Range: -40°C to +125°C |
| PLT16783 | Micropower, Regulated 3.3V/5V Charge Pump with Shutdown in SOT-23; Package: SOT; No of Pins: 6; Temperature Range: -40°C to +125°C |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PLSI1032-90LT | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
| PLSI1032E100LJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| PLSI1032E-100LJ | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
| PLSI1032E125LJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| PLSI1032E-125LJ | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic |
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