參數(shù)資料
型號： PLSI1032-90LJ
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： High-Density Programmable Logic
中文描述： EE PLD, 17 ns, PQCC84
封裝： PLASTIC, LCC-84
文件頁數(shù)： 7/19頁
文件大?。?/td> 256K
代理商： PLSI1032-90LJ
Specifications
ispLSI and pLSI 1032
7
1996 ISP Encyclopedia
UE
0.8
F S
UE
1.0
F S
Internal Timing Parameters
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
6.0
4.6
1.3
4.6
1.3
–
4.0
6.7
6.7
6.0
7.3
6.6
7.3
6.6
12.0
Outputs
t
ob
t
oen
t
odis
Clocks
t
gy0
t
gy1/2
t
gcp
t
ioy2/3
t
iocp
Global Reset
t
gr
47
48
49
50
51
52
53
54
55
Output Buffer Delay
I/O Cell OE to Output Enabled
I/O Cell OE to Output Disabled
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
Clock Delay, Y1 or Y2 to Global GLB Clock Line
Clock Delay, Clock GLB to Global GLB Clock Line
Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
Clock Delay, Clock GLB to I/O Cell Global Clock Line
Global Reset to GLB and I/O Registers
MIN. MAX.
DESCRIPTION
PARAMETER
UNITS
-60
#
2
–
–
–
4.5
3.5
1.0
3.5
–
3.0
5.0
5.0
4.5
5.5
5.0
5.5
5.0
9.0
MIN. MAX.
-80
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
–
–
–
3.6
2.8
0.8
2.8
–
2.4
4.0
4.0
3.6
4.4
4.0
4.4
4.0
8.2
MIN. MAX.
-90
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PLSI1032-90LT 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic
PLSI1032E100LJ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD
PLSI1032E-100LJ 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic
PLSI1032E125LJ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD
PLSI1032E-125LJ 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Density Programmable Logic
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