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參數(shù)資料
| 型號： | pLSI1032E-125LJ |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | High-Density Programmable Logic |
| 中文描述： | 高密度可編程邏輯 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 212K |
| 代理商： | PLSI1032E-125LJ |
5
Specifications
ispLSI and pLSI 1032E
t
pd1
t
pd2
f
max (Int.)
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
UNITS
TEST
COND.
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model
in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030A/1032E
1
4
3
1
( )
-100
MIN. MAX.
–
–
100
DESCRIPTION
#
2
PARAMETER
A
A
A
1
2
3
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay, Worst Case Path
Clock Frequency with Internal Feedback
10.0
12.5
ns
ns
MHz
–
–
–
–
4
5
6
Clock Frequency with External Feedback
Clock Frequency, Max. Toggle
GLB Reg. Setup Time before Clock,4 PT Bypass
–
–
–
MHz
MHz
ns
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
–
ns
–
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
–
ns
–
–
–
A
–
B
C
B
C
9
GLB Reg. Setup Time before Clock
GLB Reg. Clock to Output Delay
GLB Reg. Hold Time after Clock
Ext. Reset Pin to Output Delay
Ext. Reset Pulse Duration
Input to Output Enable
Input to Output Disable
Global OE Output Enable
Global OE Output Disable
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
11
12
13
14
15
16
17
–
–
–
–
–
–
–
–
t
wh
t
wl
t
su3
t
h3
–
–
18
19
External Synchronous Clock Pulse Duration, High
External Synchronous Clock Pulse Duration, Low
4.0
4.0
ns
ns
–
20
I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3)
–
ns
–
21
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
–
ns
71.0
125
7.0
0.0
8.0
0.0
6.5
3.5
0.0
6.0
7.0
13.5
15.0
15.0
9.0
9.0
–
–
( )
1
-125
MIN. MAX.
–
–
125
7.5
10.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3.0
3.0
–
–
91.0
167
5.0
0.0
6.0
0.0
5.0
3.0
0.0
5.0
6.0
10.0
12.0
12.0
7.0
7.0
–
–
External Timing Parameters
Over Recommended Operating Conditions
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