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PRELIMINARY
INVERSE MULTIPLEXING OVER ATM
PM7340 S/UNI-IMA-8
DATA SHEET
PMC-2001723
ISSUE 3
INVERSE MULTIPLEXING OVER ATM
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
137
Register 0x102: RCAS Indirect Link Data
Bit
Type
Function
Default
15:10
R
Unused
X
9
R/W
VLDLBEN
0
8
R/W
PROV
0
7:3
Unused
X
2:0
R/W
VLINK[2:0]
00
This register contains either: (1) the data read from the timeslot-provision RAM
after an indirect read operation or (2) the data to be inserted into the timeslot-
provision RAM during an indirect write operation.
The timeslot provision ram maps either timeslots from the physical links or entire
physical links to a virtual link number (VLINK). It also provisions timeslots/links
and enables the internal loopback feature.
VLINK[2:0]
The indirect data bits (VLINK[2:0]) report the virtual link number read from the
timeslot provision RAM after an indirect read operation has been completed.
The virtual link number to be written to the timeslot-provision RAM in an
indirect write operation must be set up in this register before triggering the
write. VLINK[2:0] reflects the value written until the completion of a
subsequent indirect read operation. For proper operation, timeslots in a single
link may only be mapped to a single link; in addition, only VLINK values of 0 –
0x7 are valid.
PROV
The indirect provision enable bit (PROV) reports the timeslot provision enable
flag read from the timeslot provision RAM after an indirect read operation has
been completed. The provision enable flag to be written to the timeslot
provision RAM in an indirect write operation must be set up in this register
before triggering the write. When PROV is set high, the current receive data
byte is processed as part of the virtual link (as indicated by VLINK[2:0]).
When PROV is set low, the current time-slot does not belong to any virtual
link and the receive data byte is ignored. PROV reflects the value written until
the completion of a subsequent indirect read operation.