
Head Office:
PMC-Sierra, Inc.
8555 Baxter Place
Burnaby, B.C. V5A 4V7
Canada
Tel: 604.415.6000
Fax: 604.415.6200
Frame Engine and Datalink Manager
To order documentation,
send email to:
document@pmc-sierra.com
or contact the head office,
Attn: Document Coordinator
All product documentation is available
on our web site at:
http://www.pmc-sierra.com
For corporate information,
send email to:
info@pmc-sierra.com
PMC-1991475 (p2)
Copyright PMC-Sierra, Inc. 2001.
All rights reserved. August 2001.
Any-PHY, SPECTRA-2488, TEMUX-
84, FREEDM-336A1024,SBI, and
PMC-Sierra are trademarks of
PMC-Sierra, Inc.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
Preliminary
PM7388 FREEDM 336A1024
HDLC
Support for up to 1024 bidirectional
HDLC channels, with individual HDLC
channel speeds ranging from 56 Kbps
to 52 Mbps. In a channelized
application, the number of time-slots
assigned to an HDLC channel is
programmable from 1 to 24 (for T1/J1)
and from 1 to 31 (for E1).
The 1024 HDLC channels can be
assigned to a mixture of physical links
via the 77 MHz SBI interface. The SBI
transports the equivalent of 12 STS-1
synchronous payload envelopes
(SPE). Each STS-1 SPE can be
individually configured to carry 28
T1/J1s, 21 E1s or 1 DS3.
For each channel, supports
programmable flag sequence detection
and generation, bit stuffing and de-
stuffing, and validation and generation
of either CRC-CCITT or CRC-32 frame
check sequences.
For each channel, the receiver checks
for packet abort sequences, octet
aligned packet length and for minimum
and maximum packet length.
INTERFACES
104 MHz, 8 bit Any-PHY Level 3 or 52
MHz Any-PHY Level 2 packet interface
for transfer of packet, frame or
fragment data using an external
controller. The interface is capable of
supporting full datagram transfer on a
per Any-PHY channel basis, or
fragmented packets or frames on a per
Any-PHY channel basis.
A 77 MHz SBI bus supporting up to
336 links.
12 separate clock and data interfaces
to support 12 links of arbitrary data rate
up to 52 MHz (eg, DS3/E3). The
device can be configured to process
data from either the clock and data
interfaces or from the SBI on a per
clock-data-link/SPE basis.
A 100 MHz, 48-bit SDRAM interface
for ingress and egress per
packet/fragment storage.
A 100 MHz, 32-bit SDRAM interface
for ingress re-sequencing data.
structures.
A 100 MHz, 36-bit SSRAM interface
for Ingress/Egress Context storage.
Provides a standard 5 signal P1149.1
JTAG test port for boundary scan.
A 32-bit microprocessor interface for
configuration and status monitoring.
TECHNOLOGIES
40 mm x 40 mm, 520 pin (1.27 mm
pitch) enhanced ball grid array (SBGA)
package.
Low power 0.18 mm CMOS
technology using 1.8 V core power and
3.3 V I/O.
APPLICATIONS
IETF PPP interfaces for routers.
Frame Relay interfaces for ATM or
Frame Relay switches and
multiplexers.
Internet/Intranet access equipment.
TYPICAL APPLICATION
PM5315
SPECTRA-
2488
SER
DES
PM8316
TEMUX-84
PM8316
TEMUX-84
PM8316
TEMUX-84
PM8316
TEMUX-84
PM7388
FREEDM-
336A1024
PM7388
FREEDM-
336A1024
PM7388
FREEDM-
336A1024
PM7388
FREEDM-
336A1024
TelecomBus
SBI
OC-48
OC-48 PORT CARD SOLUTION