參數(shù)資料
型號(hào): PN531
廠商: NXP Semiconductors N.V.
英文描述: Zener Diode; Application: General; Pd (mW): 400; Vz (V): 7.5 to 7.9; Condition Iz at Vz (mA): 5; C (pF) max: -; Condition VR at C (V):   ESD (kV) min: -; Package: MHD
中文描述: レ基于C傳輸模塊
文件頁(yè)數(shù): 9/19頁(yè)
文件大?。?/td> 246K
代理商: PN531
Philips Semiconductors Objective Short Form Specification Rev. 2.0 February 2004
PN531
μC based Transmission module
Pin
Symbol
Type
Pad Ref
Voltage
Description
this signal is used as test signal input.
25
SVDD
PWR
Connected to SAM power supply; used as a reference for communication
with the SAM.
26
P31
IO
PVDD
General purpose IO signal. Can be configured to act either as TX line of
the second serial interface or general purpose IO. In test mode this signal
is used as input and output test signal.
27
P30
IO
PVDD
General purpose IO signal. Can be configured to act either as RX line of
the second serial interface or general purpose IO. In test mode this signal
is used as input and output test signal.
28
IRQ
O
PVDD
Interrupt request: Output to signal an interrupt event to the host (Port 7 bit
0)
29
RSTOUT
IO
PVDD
Output reset signal. When Low it indicates that the circuit is in reset state.
30
DELATT
O
PVDD
Optional output for an external 1.5 KOhms resistor connection on D+.
31
NSS
IO
PVDD
Not Slave Select. In test mode this signal is used as input and output test
signal.
32
MOSI
IO
PVDD
Master Out Slave In. In test mode this signal is used as input and output
test signal
33
MISO
IO
PVDD
Master In Slave Out. In test mode this signal is used as input and output
test signal
34
SCK
IO
PVDD
Serial interface clock. In test mode this signal is used as input and output
test signal
35
PVDD
PWR
Pad power supply
In test mode this signal is used as input and output test signal.
General purpose IO signal. Can also be used as an interrupt source In test
mode this signal is used as input and output test signal.
36
P33_INT1
IO
PVDD
General purpose IO signal. Can be used to generate an HZ state on the
output of the selected interface for the Host communication and to enter
TAMA into power down mode without resetting the internal state of TAMA.
37
P32_INT0
IO
PVDD
38
RSTPD
I
PVDD
Reset and Power Down: When High, internal current sources are switched
off, the oscillator is inhibited, and the input pads are disconnected from the
outside world. With a positive edge on this pin the internal reset phase
starts.
39
DVDD
PWR
Digital Power Supply
40
VBUS
PWR
USB power supply.
9
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