參數(shù)資料
型號: PPC405CR-3BC266C
廠商: APPLIEDMICRO INC
元件分類: 微控制器/微處理器
英文描述: PowerPC 405CR Embedded Processor
中文描述: 32-BIT, 266.66 MHz, RISC PROCESSOR, PBGA316
封裝: 27 X 27 MM, PLASTIC, EBGA-316
文件頁數(shù): 24/42頁
文件大小: 446K
代理商: PPC405CR-3BC266C
PPC405CR – PowerPC 405CR Embedded Processor
24
AMCC
Revision 1.02 – January 11, 2005
Data Sheet
PerCS0
Peripheral chip select bank 0.
O
5V tolerant
3.3V LVTTL
7
PerCS1:7[GPIO10:16]
Seven additional peripheral chip selects
or
General Purpose I/O. To access this function, software must toggle a
DCR register bit.
O[I/O]
5V tolerant
3.3V LVTTL
1, 7
PerOE
Used by either peripheral controller or DMA controller depending
upon the type of transfer involved. When the PPC405CR is the bus
master, it enables the selected device to drive the bus.
O
5V tolerant
3.3V LVTTL
7
PerR/W
Used by the PPC405CR when not in external master mode, as output
by either the peripheral controller or DMA controller depending upon
the type of transfer involved. High indicates a read from memory, low
indicates a write to memory.
Otherwise it used by the external master as an input to indicate the
direction of transfer.
I/O
5V tolerant
3.3V LVTTL
1
PerReady
Used by a peripheral slave to indicate it is ready to transfer data.
I
5V tolerant
3.3V LVTTL
1
PerBLast
Used by the PPC405CR when not in external master mode,
otherwise used by external master. Indicates the last transfer of a
memory access.
I/O
5V tolerant
3.3V LVTTL
1, 7
DMAReq0:3
DMAReq0:3 are used by slave peripherals to indicate they are
prepared to transfer data.
I
5V tolerant
3.3V LVTTL
1
DMAAck0:3
DMAAck0:3 are used by the PPC405CR to indicate that data
transfers have occurred.
O
5V tolerant
3.3V LVTTL
6
EOT0:3/TC0:3
End Of Transfer/Terminal Count.
I/O
5V tolerant
3.3V LVTTL
1
Table 6. Signal Functional Description (Sheet 2 of 5)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 21 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull-up or pull-down required.
7. Pull-up may be required. See “External Bus Control Signals” on page 22.
Signal Name
Description
I/O
Type
Notes
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