參數(shù)資料
型號: PPC405CR-3BC266C
廠商: APPLIEDMICRO INC
元件分類: 微控制器/微處理器
英文描述: PowerPC 405CR Embedded Processor
中文描述: 32-BIT, 266.66 MHz, RISC PROCESSOR, PBGA316
封裝: 27 X 27 MM, PLASTIC, EBGA-316
文件頁數(shù): 38/42頁
文件大小: 446K
代理商: PPC405CR-3BC266C
PPC405CR – PowerPC 405CR Embedded Processor
38
AMCC
Revision 1.02 – January 11, 2005
Data Sheet
Table 15. I/O Specifications—266MHz
Notes:
1.
The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
command is used by SDRAM.
2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.
3. SDRAM interface hold times are guaranteed at the PPC405CR package pin. System designers must use the PPC405CR
IBIS model (available from
www.amcc.com
) to ensure their clock distribution topology minimizes loading and reflections,
and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.
4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
5. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Signal
Input (ns)
Output (ns)
Output Current (mA)
I/O H
(min)
Clock
Notes
Setup Time
(T
IS
min)
Hold Time
(T
IH
min)
Valid Delay
(T
OV
max)
Hold Time
(T
OH
min)
I/O L
(min)
SDRAM Interface
BA1:0
BankSel0:3
CAS
ClkEn0:1
DQM0:3
DQMCB
ECC0:7
MemAddr12:0
MemData0:31
RAS
WE
External Slave Peripheral Interface
DMAAck0:3
DMAReq0:3
EOT0:3/TC0:3
PerAddr0:31
PerBLast
PerCS0
PerCS1:7[GPIO10:16]
PerData0:31
PerOE
PerPar0:3
PerR/W
PerReady
PerWBE0:3
External Master Peripheral Interface
BusReq
ExtAck
ExtReq
ExtReset
HoldAck
HoldPri
HoldReq
PerClk
PerErr
n/a
n/a
n/a
n/a
n/a
n/a
1.5
n/a
1.5
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
1
n/a
1
n/a
n/a
5.5
4.5
5.5
3.9
4.9
4.7
4.7
5.9
4.8
5.6
5.6
1
1
1
1
1
1
1
1
1
1
1
19
19
19
40
19
19
19
19
19
19
19
12
12
12
25
12
12
12
12
12
12
12
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
1, 2
2
1, 2
2
2
2
2
1, 2
2
1, 2
1, 2
n/a
dc
dc
3
3.5
n/a
dc
dc
1
1
6
0
12
n/a
12
19
12
8
PerClk
PerClk
PerClk
PerClk
PerClk
n/a
8
8
6
n/a
0
0
0
n/a
8
12
8
n/a
n/a
6
0
12
8
PerClk
5
1
8
6
8
6
0
0
0
0
19
12
19
12
n/a
12
12
8
12
8
n/a
8
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
n/a
3.5
4
6.5
3
n/a
1
1
1
1
n/a
6
n/a
0
n/a
n/a
5
n/a
n/a
3
5
n/a
3
n/a
n/a
1
n/a
n/a
1
1
n/a
1
6
6
0
0
12
12
n/a
19
12
n/a
n/a
19
n/a
8
8
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PLB Clk
PerClk
n/a
6
6
n/a
n/a
0.9
n/a
n/a
0
0
n/a
n/a
0.9
n/a
n/a
12
8
n/a
n/a
12
n/a
4
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