- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368095 > PPC405EP-3LB133CZ (APPLIEDMICRO INC) PowerPC 405EP Embedded Processor PDF資料下載
參數(shù)資料
| 型號： | PPC405EP-3LB133CZ |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PowerPC 405EP Embedded Processor |
| 中文描述： | 32-BIT, 133.33 MHz, RISC PROCESSOR, PBGA385 |
| 封裝： | 31 X 31 MM, LEAD FREE, PLASTIC, EBGA-385 |
| 文件頁數(shù)： | 30/50頁 |
| 文件大?。?/td> | 373K |
| 代理商： | PPC405EP-3LB133CZ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁
PPC405EP – PowerPC 405EP Embedded Processor
30
AMCC
Revision 1.07 – September 10, 2007
Data Sheet
Unused I/Os
Strapping of some pins may be necessary when they are unused. Although the PPC405EP requires only the pull-
up and pull-down terminations as specified in the “Signal Functional Description” on page 31, good design practice
is to terminate all unused inputs or to configure I/Os such that they always drive. If unused, the peripheral, SDRAM,
and PCI buses should be configured and terminated as follows:
Peripheral interface—PerAddr03:31, PerData00:15, and all of the control signals are driven by default. Pull
up PerReady.
SDRAM—Program SDRAM0_CFG[EMDULR]=1 and SDRAM0_CFG[DCE]=1. This causes the PPC405EP
to actively drive all of the SDRAM address, data, and control signals.
PCI—The PCI pull-up requirements given in the Signal Functional Description apply only when the PCI
interface is being used. When the PCI bridge is unused, configure the PCI controller to park on the bus and
actively drive PCIAD31:00, PCIC3:0/BE3:0, and the remaining PCI control signals by doing the following:
- Strap the PPC405EP to disable the internal PCI arbiter.
- Individually pull up PCISErr, PCIPErr, PCITRDY, and PCIStop through 3.3k
Ω
resistors to +3.3V.
- Pull up PCIReq1:2 through a 3.3k
Ω
resistor to +3.3V.
- Pull down PCIReq0/Gnt through a 1k
Ω
resistor to GND.
External Bus Control Signals
All peripheral bus control signals (PerCS0:4, PerR/W, PerWBE0:1, PerOE, PerWE, PerBLast) are set to the high-
impedance state when ExtReset = 0. In addition, as detailed in the
PowerPC 405EP Embedded Processor User’s
Manual
, the peripheral bus controller can be programmed via EBC0_CFG to float some of these control signals
between transactions. As a result, a pull-up resistor should be added to those control signals where an undriven
state may affect any devices receiving that particular signal.
The following table lists all of the I/O signals provided by the PPC405EP. Please refer to “Signals Listed
Alphabetically” on page 13 for the pin number to which each signal is assigned.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PPC405EP-3LB200C | PowerPC 405EP Embedded Processor |
| PPC405EP-3LB200CZ | PowerPC 405EP Embedded Processor |
| PPC405EP-3LB266C | PowerPC 405EP Embedded Processor |
| PPC405EP-3LB266CZ | PowerPC 405EP Embedded Processor |
| PPC405EP-3LB333C | PowerPC 405EP Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC405EP-3LB200C | 制造商:AppliedMicro 功能描述:AMCPPC405EP-3LB200C 32 Bit PowerPC |
| PPC405EP-3LB200CZ | 制造商:AppliedMicro 功能描述:MPU 405EP RISC 32-Bit 0.18um 200MHz 3.3V 385-Pin EBGA T/R |
| PPC405EP-3LB266C | 制造商:AppliedMicro 功能描述:MPU 405EP RISC 32-Bit 0.18um 266MHz 3.3V 385-Pin EBGA Tray 制造商:AMCC 功能描述:MPU 405EP RISC 32BIT 0.18UM 266MHZ 3.3V 385PIN EBGA - Trays 制造商:AMCC 功能描述:AMCPPC405EP-3LB266C 32BIT PPC UP TO 333M 制造商:Applied Micro Circuits Corporation 功能描述:MPU 405EP RISC 32-Bit 0.18um 266MHz 3.3V 385-Pin EBGA Tray |
| PPC405EP-3LB266CZ | 制造商:AppliedMicro 功能描述:MPU 405EP RISC 32-Bit 0.18um 266MHz 3.3V 385-Pin EBGA T/R 制造商:AMCC 功能描述:AMCPPC405EP-3LB266CZ 32B MPU EOL040910 |
| PPC405EP-3LB333C | 制造商:AMCC 功能描述:MPU 405EP RISC 32BIT 0.18UM 333MHZ 3.3V 385BGA - Trays 制造商:AMCC 功能描述:AMCPPC405EP-3LB333C 32 BIT POWER PCCORE |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。