參數(shù)資料
型號: PPC405EP-3LB133CZ
廠商: APPLIEDMICRO INC
元件分類: 微控制器/微處理器
英文描述: PowerPC 405EP Embedded Processor
中文描述: 32-BIT, 133.33 MHz, RISC PROCESSOR, PBGA385
封裝: 31 X 31 MM, LEAD FREE, PLASTIC, EBGA-385
文件頁數(shù): 46/50頁
文件大?。?/td> 373K
代理商: PPC405EP-3LB133CZ
PPC405EP – PowerPC 405EP Embedded Processor
46
AMCC
Revision 1.07 – September 10, 2007
Data Sheet
Internal Peripheral Interface
IICSCL
IICSDA
UART0_CTS
UART0_RTS
UART0_Rx
UART0_Tx
UART1_Rx
UART1_Tx
Interrupts Interface
[IRQ0:6]
JTAG Interface
TCK
TDI
TDO
TMS
TRST
System Interface
GPIO00:31
Halt
SysErr
SysReset
TestEn
[RejectPkt0:1]
SysClk
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
15.3
15.3
na
10.3
na
10.3
na
10.3
10.2
10.2
na
7.1
na
7.1
na
7.1
10.3
7.1
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
10.3
na
na
na
na
7.1
na
na
async
async
async
async
async
na
na
na
na
na
3
na
na
na
na
na
na
1
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
10.3
na
10.3
10.3
na
na
na
7.1
na
7.1
7.1
na
na
na
async
async
async
async
async
Table 14. I/O Specifications—Group 1 (Sheet 2 of 2)
Notes:
1.
PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns
for 33.33MHz.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter
selected. See the CPC0_EPCTL register
PowerPC 405EP Embedded Processor User’s Manual
.
3. For PCI, I
OH
is specified at 0.9OV
DD
and I
OL
is specified at 0.1OV
DD
. For all other interfaces, I
OH
is specified at 2.4V and I
OL
is specified at 0.4V.
Signal
Input (ns)
Output (ns)
Output Current (mA)
I
OH
(min)
Clock
Notes
Setup Time
(T
IS
min)
Hold Time
(T
IH
min)
Valid Delay
(T
OV
max)
Hold Time
(T
OH
min)
I
OL
(min)
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