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14
AMCC Proprietary
440EP – PPC440EP Embedded Processor
Revision 1.26 – April 25, 2007
Data Sheet
Serial Peripheral Interface (SPI/SCP)
The Serial Peripheral Interface (also known as the Serial Communications Port) is a full-duplex, synchronous,
character-oriented (byte) port that allows the exchange of data with other serial devices. The SCP is a master on
the serial port supporting a 3-wire interface (receive, transmit, and clock), and is a slave on the OPB.
Features include:
Three-wire serial port interface
Full-duplex synchronous operation
SCP bus master
OPB bus slave
Programmable clock rate divider
Clock inversion
Reverse data
Local data loop back for test
Universal Serial Bus (USB)
The USB interfaces provide both device and host support for version 1.1 and device support for version 2.0.
Support for the USB 2.0 Transceiver Macrocell Interface (UTMI) specification is included.
Features include:
USB 1.1 Host port with internal PHY
USB 2.0 Device UTMI or USB 1.1 Device PHY
Device support provides 6 end points (3 in, 3 out)
1024B FIFO (double buffering of 512B packets)
FIFOs are
not
shared between in and out endpoints
Endpoints
do not
support high-bandwidth isochronous transfers
Two USB 2.0 device end points have DMA dedicated channels (DMA to PLB 128)
NAND Flash Controller
The NAND Flash controller provides a simple interface between the EBC and up to four separate external NAND
Flash devices. It provides both direct command, address, and data access to the external device as well as a
memory-mapped linear region that generates data accesses. NAND Flash device data appears on the peripheral
data bus.
Features include:
1 to 4 banks supported on EBC
Direct Interfacing to:
– Discrete NAND Flash devices (up to 4 devices)
– SmartMedia Card socket (22-pins)
Device sizes 4MB-256MB supported
(512 + 16)-B or (2K + 64)-B device page sizes supported
Boot-from-NAND: Execute a linear sequence of boot code out of single page of first block (512B)
Support DMA to allow direct, no-processor-intervention block copy from NAND Flash to SDRAM
ECC provides single-bit error correction and double-bit error detection in each 256B of stored data
Chip selects shared with EBC