參數(shù)資料
型號(hào)： PPC440EPx-NpAfffTs
廠商： Applied Micro Circuits Corp.
英文描述： PowerPC 440EPx Embedded Processor
中文描述： 嵌入式處理器的PowerPC 440EPx
文件頁數(shù)： 57/94頁
文件大?。?/td> 738K
代理商： PPC440EPX-NPAFFFTS
440EPx – PPC440EPx Embedded Processor
Revision 1.26 – October 15, 2007
Preliminary Data Sheet
AMCC Proprietary
57
Table 8. Signal Functional Description (Sheet 1 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3 k
Ω
to OV
DD
(EOV
DD
for Ethernet)
3. Must pull down (recommended value is 1 k
Ω
)
4. If not used, must pull up (recommended value is 3 k
Ω
to OV
DD
(EOV
DD
for Ethernet)
5. If not used, must pull down (recommended value is 1 k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
PCI Interface
PCIAD00:31
Address/Data bus (bidirectional).
I/O
3.3 V PCI
PCIC0:3/BE0:3
PCI Command/Byte Enables
.
I/O
3.3 V PCI
PCIClk
Provides timing to the PCI interface for PCI transactions.
I
3.3 V PCI
1, 5
PCIDevSel
Indicates the driving device has decoded its address as the
target of the current access.
(PCI 2.2 specification requires 8.2K
Ω
pull up on host system)
I/O
3.3 V PCI
PCIFrame
Driven by the current master to indicate beginning and duration
of an access.
(PCI 2.2 specification requires 8.2K
Ω
pull up on host system)
I/O
3.3 V PCI
PCIGnt0/Req
Indicates that the specified agent is granted access to the bus.
When the internal arbiter is enabled, output is PCIGnt0. When
the internal arbiter is disabled, output is Req.
(PCI 2.2 specification requires 8.2K
Ω
pull up on host system)
O
3.3 V PCI
PCIGnt1:5
Indicates that the specified agent is granted access to the bus.
Used only when internal PCI arbiter enabled.
O
3.3 V PCI
PCIIDSel
Used as a chip select during configuration read and write
transactions.
I
3.3 V PCI
PCIINT
Level sensitive PCI interrupt.
O
3.3 V PCI
PCIIRDY
Indicates initiating agent’s ability to complete the current data
phase of the transaction.
(PCI 2.2 specification requires 8.2K
Ω
pull up on host system)
I/O
3.3 V PCI
PCIPar
Even parity.
I/O
3.3 V PCI
PCIPErr
Reports data parity errors during all PCI transactions except a
Special Cycle.
(PCI 2.2 specification requires 8.2K
Ω
pull up on host system)
I/O
3.3 V PCI
PCIReq0/Gnt
Indicates to the PCI arbiter that the specified agent wishes to use
the bus. When the internal arbiter is enabled, input is PCIReq0.
When internal arbiter is disabled, input is Gnt.
I
3.3 V PCI
1, 4
PCIReq1:5
An indication to the PCI arbiter that the specified agent wishes to
use the bus. Used only when internal PCI arbiter enabled.
I
3.3 V PCI
1, 4
PCIReset
Brings PCI device registers and logic to a consistent state.
O
3.3 V PCI
PCISErr
Reports address parity errors, data parity errors on the Special
Cycle command, or other catastrophic system errors.
(PCI 2.2 specification requires 8.2K
Ω
pull up on host system)
I/O
3.3 V PCI
PCIStop
Indicates the current target is requesting the master to stop the
current transaction.
(PCI 2.2 specification requires 8.2K
Ω
pull up on host system)
I/O
3.3 V PCI
PCITRDY
I
ndicates the target agent’s ability to complete the current data
phase of the transaction.
(PCI 2.2 specification requires 8.2K
Ω
pull up on host system)
I/O
3.3 V PCI
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PPC440EPX-NTA400E 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays
PPC440EPX-NTA400EZ 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel
PPC440EPX-NTA533E 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays
PPC440EPX-NTA533EZ 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel
PPC440EPX-NTA667E 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays
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