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參數(shù)資料
| 型號： | PPC440EPx-SpAfffTs |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 440EPx Embedded Processor |
| 中文描述： | 嵌入式處理器的PowerPC 440EPx |
| 文件頁數(shù)： | 62/94頁 |
| 文件大?。?/td> | 738K |
| 代理商： | PPC440EPX-SPAFFFTS |
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440EPx – PPC440EPx Embedded Processor
Preliminary Data Sheet
62
AMCC Proprietary
Revision 1.26 – October 15, 2007
USB UTMI Peripheral Interface
USB2DI7:0
Unidirectional data inputs.
I/O
3.3V LVTTL
USB2DO7:0
Unidirectional data outputs.
I/O
3.3V LVTTL
USB2TxRdy
Transmit data ready.
I
3.3V LVTTL
w/pull-down
USB2RxAct
Receive active.
I
3.3V LVTTL
USB2RxDV
Receive valid.
I/O
3.3V LVTTL
w/pull-up
1
USB2RxErr
Receive error.
I/O
3.3V LVTTL
1
USB2LS0:1
Line state 0 and Line state 1.
I
3.3V LVTTL
w/pull-up
USB2TxVal
Transmit valid.
I/O
3.3V LVTTL
1
USB2Susp
Suspend.
I/O
3.3V LVTTL
1
USB2XcvrSel
Transceiver select.
I/O
3.3V LVTTL
1
USB2TermSel
Termination select.
I/O
3.3V LVTTL
1
USB2OM0:1
Operational mode.
I/O
3.3V LVTTL
1
USB2Clk
USB 2.0 Clock (60 MHz).
I
3.3V LVTTL
1, 5
USB PHY Peripheral Interface
USB2Xcvr
USB2Xcvr
USB 2.0 differential transceiver.
I/O
5 V tolerant
Analog
5
USB2XtalIn
USB2XtalOut
USB 2.0 external crystal (48 MHz) or external oscillator (48 MHz).
External crystal:
In/Out differential must not be less than
500 mV.
External oscillator:
Connect oscillator with signal swing of 3.3 V
between USB2XtalOut and ground.
See
Table 19
on page 76.
I/O
Analog
USB2RExt
External resistor connection for bias current.
Use 3.4 k
Ω
, 1% resistor connected to GND.
I/O
Analog
NAND Flash Interface
NFALE
Address Latch Enable.
O
3.3V LVTTL
1
NFCE0:3
Chip Enable (multiplexed with the PerCS0:3 signals).
O
3.3V LVTTL
1
NFCLE
Command Latch Enable.
Latches operational commands into the NAND Flash.
O
3.3V LVTTL
1
NFRdyBusy
Ready/Busy.
Indicates status of device during program erase or page read.
This signal is wire-OR connected from all NAND Flash devices.
I
3.3V LVTTL
1
NFREn
Read Enable.
Data is latched on the rising edge.
O
3.3V LVTTL
1
NFWEn
Write Enable.
Data is latched on the rising edge.
O
3.3V LVTTL
1
Table 8. Signal Functional Description (Sheet 6 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3 k
Ω
to OV
DD
(EOV
DD
for Ethernet)
3. Must pull down (recommended value is 1 k
Ω
)
4. If not used, must pull up (recommended value is 3 k
Ω
to OV
DD
(EOV
DD
for Ethernet)
5. If not used, must pull down (recommended value is 1 k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
相關PDF資料 |
PDF描述 |
|---|---|
| PPC440EP | Power PC 440EP Embedded Processor |
| PPC440EP-3pbfffCx | Power PC 440EP Embedded Processor |
| PPC440GP-3CC333C | Power PC 440GP Embedded Processor |
| PPC440GP-3CC400C | Power PC 440GP Embedded Processor |
| PPC440GP-3CC400CZ | Power PC 440GP Embedded Processor |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440EPX-STA400E | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
| PPC440EPX-STA400EZ | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
| PPC440EPX-STA533E | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
| PPC440EPX-STA533EZ | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
| PPC440EPX-STA667E | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
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