參數資料
型號: PPC440EPx-SpAfffTs
廠商: Applied Micro Circuits Corp.
英文描述: PowerPC 440EPx Embedded Processor
中文描述: 嵌入式處理器的PowerPC 440EPx
文件頁數: 78/94頁
文件大小: 738K
代理商: PPC440EPX-SPAFFFTS
440EPx – PPC440EPx Embedded Processor
Preliminary Data Sheet
78
AMCC Proprietary
Revision 1.26 – October 15, 2007
TmrClk frequency
100
MHz
TmrClk period
10
ns
TmrClk high time
40% of nominal period
60% of nominal period
ns
TmrClk low time
40% of nominal period
60% of nominal period
ns
Notes:
1. T
OPB
is the period in ns of the OPB clock. The internal OPB clock runs at 1/2 the frequency of the PLB clock. The maximum OPB clock
frequency is 83 MHz.
2. An internal PLL improves this duty cycle to a worst case of 48% minimum, 52% maximum.
3. Crystals, external clocks, or external oscillators must have a maximum tolerance of ±100 ppm and maximum jitter of ±100 ps.Only a
frequencies of 48 MHz is allowed for oscillators; only a frequencies of 48 MHz is allowed for crystals. Crystals and oscillators should be
connected as shown below:
PPC440EPx
C
C
Crystal
USB2XtalIn
PPC440EPx
Osc
USB2XtalOUT
USB2XtalOut
USB2XtalIn
C = 2(C
L
C
Stray
) where
C
L
is the load capacitance required by the crystal for oscillation
C
Stray
is the board parasitic capacitance
Crystal – Frequency: 48MHz
Resonance mode: parallel
C
O
: 15–30pF
ESR: 20-60
Ω
Drive level: 50–500
μ
W
Table 19. Peripheral Interface Clock Timings (Sheet 3 of 3)
Parameter
Min
Max
Units
Notes
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