參數(shù)資料
型號： PPC440GP-3RC500C
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： Power PC 440GP Embedded Processor
中文描述： 32-BIT, 500 MHz, RISC PROCESSOR, CBGA552
封裝： 25 X 25 MM, ROHS COMPLIANT, CERAMIC, BGA-552
文件頁數(shù)： 50/83頁
文件大?。?/td> 773K
代理商： PPC440GP-3RC500C
440GP – Power PC 440GP Embedded Processor
50
AMCC
Revision 1.07 – October 4, 2007
Data Sheet
EMCTxEn,
EMC0TxEn
MII: Transmit data enabled
RMII 0: Transmit data enabled
O
5V tolerant
3.3V LVTTL
EMCTxErr,
EMC1TxEn
MII: Transmit error:
RMII: Transmit data enabled
O
5V tolerant
3.3V LVTTL
External Slave Peripheral Interface
DMAAck0:3
Used by the PPC440GP to indicate that data transfers have
occurred.
O
5V tolerant
3.3V LVTTL
DMAReq0:3
Used by slave peripherals to indicate they are prepared to transfer
data.
I
5V tolerant
3.3V LVTTL
1, 5
EOT0:3/TC0:3
End Of Transfer/Terminal Count.
I/O
5V tolerant
3.3V LVTTL
1, 5
PerAddr00:31
Peripheral address bus used by PPC440GP when not in external
master mode, otherwise used by external master.
Note:
PerAddr00 is the most significant bit (msb) on this bus.
I/O
5V tolerant
3.3V LVTTL
1
PerWBE0:3
External peripheral data bus byte enables.
I/O
5V tolerant
3.3V LVTTL
1, 2
PerBLast
Used by either the peripheral controller, DMA controller, or
external master to indicates the last transfer of a memory access.
I/O
5V tolerant
3.3V LVTTL
1, 4
PerCS0:7
External peripheral device select.
O
5V tolerant
3.3V LVTTL
2
PerData00:31
Peripheral data bus used by PPC440GP when not in external
master mode, otherwise used by external master.
Note:
PerData00 is the most significant bit (msb) on this bus.
I/O
5V tolerant
3.3V LVTTL
1
PerOE
Used by either peripheral controller or DMA controller depending
upon the type of transfer involved. When the PPC440GP is the
bus master, it enables the selected device to drive the bus.
O
5V tolerant
3.3V LVTTL
2
PerPar0:3
External peripheral data bus byte parity.
I/O
5V tolerant
3.3V LVTTL
1
PerReady
Used by a peripheral slave to indicate it is ready to transfer data.
I
5V tolerant
3.3V LVTTL
PerR/W
Used by the PPC440GP when not in external master mode, as
output by either the peripheral controller or DMA controller
depending upon the type of transfer involved. High indicates a
read from memory, low indicates a write to memory.
Otherwise, it used by the external master as an input to indicate
the direction of transfer.
I/O
5V tolerant
3.3V LVTTL
1, 2
PerWE
Write Enable. Low when any of the four PerWBE0:3 signals are
low.
O
5V tolerant
3.3V LVTTL
2
Signal Functional Description
(Sheet 3 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω
to 3.3V, 10k
Ω
to 5V
)
3. Must pull down (recommended value is 1k
Ω
)
4. If not used, must pull up (recommended value is 3k
Ω
to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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