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參數(shù)資料
| 型號(hào)： | PPC440GP-3RC500CZ |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Power PC 440GP Embedded Processor |
| 中文描述： | 32-BIT, 500 MHz, RISC PROCESSOR, CBGA552 |
| 封裝： | 25 X 25 MM, ROHS COMPLIANT, CERAMIC, BGA-552 |
| 文件頁(yè)數(shù)： | 14/83頁(yè) |
| 文件大小： | 773K |
| 代理商： | PPC440GP-3RC500CZ |
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440GP – Power PC 440GP Embedded Processor
14
AMCC
Revision 1.07 – October 4, 2007
Data Sheet
IIC Bus Interface
Features include:
Two IIC interfaces provided
Support for Philips Semiconductors I
2
C Specification, dated 1995
Operation at 100kHz or 400kHz
8-bit data
10- or 7-bit address
Slave transmitter and receiver
Master transmitter and receiver
Multiple bus masters
Supports fixed V
DD
IIC interface
Two independent 4 x 1 byte data buffers
Twelve memory-mapped, fully programmable configuration registers
One programmable interrupt request signal
Provides full management of all IIC bus protocols
Programmable error recovery
General Purpose Timers (GPT)
Provides a separate time base counter and additional system timers in addition to those defined in the processor
core.
32-bit Time Base Counter driven by the OPB bus clock
Five 32-bit compare timers
General Purpose IO (GPIO) Controller
Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master
accesses.
31 of the 32 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO
capabilities acts as a GPIO or is used for another purpose.
Each GPIO output is separately programmable to emulate an open drain driver (that is, drives to zero,
tri-stated if output bit is 1).
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