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參數(shù)資料
| 型號： | PPC440SP-RNC667C |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PowerPC 440SP Embedded Processor |
| 中文描述： | 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783 |
| 封裝： | 29 X 29 MM, 1 MM PITCH, ROHS COMPLIANT, PLASTIC, FCBGA-783 |
| 文件頁數(shù)： | 14/85頁 |
| 文件大?。?/td> | 615K |
| 代理商： | PPC440SP-RNC667C |
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PowerPC 440SP Embedded Processor
14
AMCC Proprietary
Revision 1.23 - Sept 26, 2006
Data Sheet
Features include:
Two IIC interfaces provided
Support for Philips
Semiconductors I
2
C Specification, dated 1995
Operation at 100kHz or 400kHz
8-bit data
10- or 7-bit address
Slave transmitter and receiver
Master transmitter and receiver
Multiple bus masters
Supports fixed V
DD
IIC interface
Two independent 4 x 1 byte data buffers
Twelve memory-mapped, fully programmable configuration registers
One programmable interrupt request signal
Full management of all IIC bus protocols
Programmable error recovery
Port 0 supports serial Bootstrap ROM with default parameters override at initialization
General Purpose Timers (GPT)
Provides a time base counter and system timers additional to those defined in the processor core.
32-bit time base counter driven by the OPB bus clock
Seven 32-bit compare timers
General Purpose IO (GPIO) Controller
Controller functions and GPIO registers are programmed and accessed by means of memory-mapped OPB
bus master accesses.
The 32 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO
capabilities acts as a GPIO or is used for another purpose.
Each GPIO output is a separately programmable tri-state driver (pull-up, pull-down, or open-drain).
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