- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄368097 > PPC440SP (Applied Micro Circuits Corp.) PowerPC 440SP Embedded Processor PDF資料下載
參數(shù)資料
| 型號(hào)： | PPC440SP |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 440SP Embedded Processor |
| 中文描述： | 嵌入式處理器的PowerPC 440SP |
| 文件頁(yè)數(shù)： | 5/85頁(yè) |
| 文件大?。?/td> | 615K |
| 代理商： | PPC440SP |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)當(dāng)前第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)
PowerPC 440SP Embedded Processor
Revision 1.23 - Sept 26, 2006
Data Sheet
AMCC Proprietary
5
PPC440SP Functional Block Diagram
Figure 2. PPC440SP Functional Block Diagram
The PPC440SP is a System on a chip, which uses IBM
CoreConnect
Bus Architecture.
Implemented with the Crossbar option, the IBM CoreConnect buses provide:
128-bit Data, 64-bit Address PLB interfaces up to 166.66MHz, 2.6GB/s on both the Read and Write data
paths (10.6GB/sec total)
32-bit OPB interfaces up to 83.33MHz, 333MB/s
Address Maps
The PPC440SP incorporates two address maps. The first is a fixed processor system memory address map. This
address map defines the possible contents of various processor accessible address regions. The second address
map identifies the system Device Configuration Registers (DCRs). DCRs are accessed by software running on the
PPC440SP processor through the use of
mtdcr
and
mfdcr
instructions.
UART2
UART1
IIC1
Processor Core
DCR Bus
32KB
I-Cache
On-chip Peripheral Bus (OPB)
GPIO
Accelerator
Unit
(DMA2)
Bridge
DDR2 SDRAM
Controller
External
Bus Controller
(EBC)
Clock,
Control,
Reset
Power
Mgmt
JTAG
Timers
MMU
OPB
Interrupt
Controller
Universal
32KB
D-Cache
XOR/DMA
PPC440
DDR PCI-X
PCI1
MAL
Ethernet
10/100/
1000
(EMAC)
DCRs
GPT
L2 Cache/SRAM
Low Latency (LL) Segment
High Bandwidth (HB) Segment
Controller
(DMA0 and
DMA1)
Processor Local Bus (PLB)
Trace
Arbiter
PLB
I2O/DMA
Host
64 bits
Local
64 bits
Local
32 bits
Memory
Queue
PCI0
PCI2
MII,
GMII
IIC0
UART0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PPC440SP-AFC533C | PowerPC 440SP Embedded Processor |
| PPC440SP-AFC667C | PowerPC 440SP Embedded Processor |
| PPC440SP-ANC533C | PowerPC 440SP Embedded Processor |
| PPC440SP-ANC667C | PowerPC 440SP Embedded Processor |
| PPC440SP-RFC533C | PowerPC 440SP Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440SP-3FB533C | 制造商:AMCC 功能描述: 制造商:AppliedMicro 功能描述: |
| PPC440SP-AFC533C | 制造商:AMCC 功能描述:AMCPPC440SP-AFC533C POWER PC |
| PPC440SP-AFC667C | 制造商:AMCC 制造商全稱(chēng):Applied Micro Circuits Corporation 功能描述:PowerPC 440SP Embedded Processor |
| PPC440SP-ANC533C | 制造商:AMCC 制造商全稱(chēng):Applied Micro Circuits Corporation 功能描述:PowerPC 440SP Embedded Processor |
| PPC440SP-ANC667C | 制造商:AMCC 制造商全稱(chēng):Applied Micro Circuits Corporation 功能描述:PowerPC 440SP Embedded Processor |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。