參數(shù)資料
型號(hào)： PR31100ABC
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： Highly integrated embedded processor
中文描述： 32-BIT, RISC MICROCONTROLLER, PQFP208
文件頁(yè)數(shù)： 4/26頁(yè)
文件大?。?/td> 282K
代理商： PR31100ABC
Philips Semiconductors
Preliminary specification
MIPS
PR31100
Highly integrated embedded processor
1996 Aug 07
4
OVERVIEW
Each of the on-chip peripherals consist of:
BIU Module
System memory and PR31100 Bus Interface Unit (BIU)
–
supports up to 2 banks of physical memory
–
supports self–refreshing DRAM and SDRAM
–
programmable parameters for each bank of DRAM or SDRAM
(row/column address configuration, refresh, burst modes, etc.)
programmable chip select memory access
–
4 programmable (size, wait states, burst mode control) memory
device and general purpose chip selects
available for system ROM, SRAM, Flash
available for external port expansion registers
–
4 programmable (wait states, burst mode control) MagicCard or
general purpose chip selects
available for (future) MagicCard expansion memory
PR31100 provides the chip select and card detect signals
supports card insertion/removal timeouts
MagicCard requires minimal number of unique control/status
signals per port
supports up to 2 identical full PCMCIA ports
–
PR31100 and UCB1100 provide the control signals and accepts
the status signals which conform to the PCMCIA version 2.01
standard
–
appropriate connector keying and level–shifting buffers required
for 3.3V versus 5V PCMCIA interface implementations
SIU Module
multi–channel 32–bit DMA controller and System Interface Unit
(SIU)
independent DMA channels for video, Magicbus, SIB to/from
UCB1100 audio/telecom codecs, high–speed serial port, IR UART,
and general purpose UART
address decoding for submodules within System Interface Module
(SIM)
CPU Module
R3000 RISC central processing unit core
–
full 32–bit operation (registers, instructions, addresses)
–
32 general purpose 32–bit registers; 32–bit program counter
–
MIPS RISC Instruction Set Architecture (ISA) supported
on–chip cache
–
4 KByte direct–mapped instruction cache (I–cache)
physical address tag and valid bit per cache line
programmable burst size
instruction streaming mode supported
–
1 KByte data cache (D–cache)
physical address tag and valid bit per cache line
programmable burst size
write–through
–
cache address snoop mode supported for DMA
–
4–level deep write buffer
programmable memory protection
–
separate read and write protection control for kernel and user
space
–
8 total protectable regions available, each individually
programmable, using breakpoint address, mask, control, and
status registers
–
causes address exception on illegal reads or writes
high–speed multiplier/accumulator
–
on–chip hardware multiplier
–
supports 16x16 or 32x32 multiplier operations, with 64–bit
accumulator
–
existing multiply instructions are enhanced and new multiply
and add instructions are added to R3000 instruction set to
improve the performance of DSP applications
CPU interface
–
handles data bus, address bus, and control interface between
CPU core and rest of PR31100 logic
Clock Module
PR31100 supports system–wide single crystal configuration,
besides the 32 KHz RTC XTAL (reduces cost, power, and board
space)
common crystal rate divided to generate clock for CPU, video,
sound, telecom, UARTs, etc.
external system crystal rate is vendor–dependent
independent enabling or disabling of individual clocks under
software control, for power management
CHI Module
high–speed serial Concentration Highway Interface (CHI) contains
logic for interfacing to external full–duplex serial
time–division–multiplexed (TDM) communication peripherals
supports ISDN line interface chips and other PCM/TDM serial
devices
CHI interface is programmable (number of channels, frame rate,
bit rate, etc.) to provide support for a variety of formats
supports data rates up to 4.096 Mbps
independent DMA support for CHI receive and transmit
Interrupt Module
contains logic for individually enabling, reading, and clearing all
PR31100 interrupt sources
interrupts generated from internal PR31100 modules or from edge
transitions on external signal pins
IO Module
contains support for reading and writing the 7 bi–directional
general purpose IO pins and the 32 bi–directional multi–function
IO pins
each IO port can generate a separate positive and negative edge
interrupt
independently configurable IO ports allow PR31100 to support a
flexible and wide range of system applications and configurations
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