參數(shù)資料
型號(hào)： PR31100ABC
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Highly integrated embedded processor
中文描述： 32-BIT, RISC MICROCONTROLLER, PQFP208
文件頁(yè)數(shù)： 9/26頁(yè)
文件大小： 282K
代理商： PR31100ABC
Philips Semiconductors
Preliminary specification
MIPS
PR31100
Highly integrated embedded processor
1996 Aug 07
9
PIN #
NAME AND FUNCTION
TYPE
NAME
Memory Pins
(continued)
117, 118
/CARD1CSH,L
O
These pins are the Chip Select signals for PCMCIA card slot 1.
112
/CARDREG
O
This pin is the /REG signal for the PCMCIA cards.
110
/CARDIORD
O
This pin is the /IORD signal for the PCMCIA IO cards.
111
/CARDIOWR
O
This pin is the /IOWR signal for the PCMCIA IO cards.
115
/CARDDIR
O
This pin is used to provide the direction control for bi–directional data buffers used for the PCMCIA
slot(s). This signal will assert whenever /CARD2CSH or /CARD2CSL or /CARD1CSH or
/CARD1CSL is asserted and a read transaction is taking place.
105
/CARD2WAIT
I
This pin is the card wait signal from PCMCIA card slot 2.
113
/CARD1WAIT
I
This pin is the card wait signal from PCMCIA card slot 1.
Bus Arbitration Pins
167
/DREQ
I
This pin is used to request external arbitration. If the TESTSIU signal is high and the TESTSIU
function has been enabled, then once /DGRNT is asserted, external logic can initiate reads or
writes to PR31100 processor registers by driving the appropriate input signals. If the TESTSIU
signal is low or the TESTSIU function has not been enabled, then PR31100 memory transactions
are halted and certain memory signals will be tri–stated when /DGRNT is asserted in order to allow
an external master to access memory.
166
/DGRNT
O
This pin is asserted in response to /DREQ to inform the external test logic or bus master that it can
now begin to drive signals.
Clock Pins
128
SYSCLKIN
I
This pin should be connected along with SYSCLKOUT to an external crystal which is the main
PR31100 clock source.
129
SYSCLKOUT
O
This pin should be connected along with SYSCLKIN to an external crystal which is the main
PR31100 clock source.
79
C32KIN
I
This pin along with C32KOUT should be connected to a 32.768 KHz crystal.
80
C32KOUT
O
This pin along with C32KIN should be connected to a 32.768 KHz crystal.
77
BC32K
O
This pin is a buffered output of the 32.768 KHz clock.
CHI Pins
50
CHIFS
I/O
This pin is the CHI frame synchronization signal. This pin is available for use in one of two modes.
As an output, this pin allows PR31100 to be the master CHI sync source. As an input, this pin
allows an external peripheral to be the master CHI sync source and the PR31100 CHI module will
slave to this external sync.
49
CHICLK
I/O
This pin is the CHI clock signal. This pin is available for use in one of two modes. As an output,
this pin allows PR31100 to be the master CHI clock source. As an input, this pin allows an
external peripheral to be the master CHI clock source and the PR31100 CHI module will slave to
this external clock.
52
CHIDOUT
O
This pin is the CHI serial data output signal.
51
CHIDIN
I
This pin is the CHI serial data input signal.
IO Pins
46, 107,
47, 108,
56, 64,
64
IO(6:0)
I/O
These pins are general purpose input/output ports. Each port can be independently programmed
as an input or output port. Each port can generate a separate positive and negative edge interrupt.
Each port can also be independently programmed to use a 16 to 24 msec debouncer.
30, 45
MFIO(1:0)
I/O
These pins are multi–function input/output ports. Each port can be independently programmed as
an input or output port, or can be programmed for multi–function use to support vendor–dependent
test signals (for debugging purposes only). Each port can generate a separate positive and
negative edge interrupt. Note that 30 other multi–function pins are available for usage as
multi–function input/output ports. These pins are named after their respective standard/normal
function and are not listed here.
Magicbus Pins
34
MBUSCLK
I/O
This pin is the bi–directional Magicbus clock signal. MBUSCLK is an input signal whenever
PR31100 is in the slave mode and is an output signal whenever PR31100 is in the master mode.
32
MBUSDATA
I/O
This pin is the bi–directional Magicbus data signal. MBUSDATA is an input signal whenever
PR31100 is in the slave mode and is an output signal whenever PR31100 is in the master mode.
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