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參數(shù)資料
| 型號： | PR31500ABC |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Poseidon embedded processor |
| 中文描述： | RISC PROCESSOR, PQFP208 |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 277K |
| 代理商： | PR31500ABC |
Philips Semiconductors
Preliminary specification
MIPS
PR31500
Poseidon embedded processor
1996 Sep 24
10
PIN #
NAME AND FUNCTION
TYPE
NAME
Reset Pins
88
/CPURES
I
This pin is used to reset the CPU core. This pin should be connected to a switch for initiating a
reset in the event that a software problem might hang the CPU core. The pin should also be pulled
up to VSTANDBY through an external pull-up resistor.
87
/PON
I
This pin serves as the Power On Reset signal for PR31500. This signal must remain low when
VSTANDBY is asserted until VSTANDBY is stable. Once VSTANDBY is asserted, this signal
should never go low unless all power is lost in the system.
Power Supply Pins
86
ONBUTN
I
This pin is used as the On Button for the system. Asserting this signal will cause PWRCS to set to
indicate to the System Power Supply to turn power on to the system. PWRCS will not assert if the
PWROK signal is low.
82
PWRCS
O
This pin is used as the chip select for the System Power Supply. When the system is off, the
assertion of this signal will cause the System Power Supply to turn VCCDRAM and VCC3 on to
power up the system. The Power Supply will latch SPI commands on the falling edge of PWRCS.
84
PWROK
I
This pin provides a status from the System Power Supply that there is a good source of power in
the system. This signal typically will be asserted if there is a Battery Charger supplying current or
if the Main Battery is good and the Battery Door is closed. If PWROK is low when the system is
powered off, PWRCS will not assert as a result of the user pressing the ONBUTN or an interrupt
attempting to wake up the system. If the device is on when the PWROK signal goes low, the
software will immediately shut down the system since power is about to be lost. When PWROK
goes low, there must be ample warning so that the software can shut down the system before
power is actually lost.
83
PWRINT
I
This pin is used by the System Power Supply to alert the software that some status has changed
in the System Power Supply and the software should read the status from the System Power
Supply to find out what has changed. These will be low priority events, unlike the PWROK status,
which is a high priority emergency case.
76
VCC3
I
This pin provides the status of the power supply for the ROM, UCB1100, system buffers, and other
transient components in the system. This signal will be asserted by the System Power Supply
when PWRCS is asserted, and will always be turned off when the system is powered down.
SIB Pins
41
SIBDIN
I
This pin contains the input data shifted from UCB1100 and/or external codec device.
42
SIBDOUT
O
This pin contains the output data shifted to UCB1100 and/or external codec device.
39
SIBSCLK
O
This pin is the serial clock sent to UCB1100 and/or external codec device. The programmable
SIBSCLK rate is derived by dividing down from SIBMCLK.
40
SIBSYNC
O
This pin is the frame synchronization signal sent to UCB1100 and/or external codec device. This
frame sync is asserted for one clock cycle immediately before each frame starts and all devices
connected to the SIB monitor SIBSYNC to determine when they should transmit or receive data.
44
SIBIRQ
I
This pin is a general purpose input port used for the SIB interrupt source from UCB1100. This
interrupt source can be configured to generate an interrupt on either a positive and/or negative
edge.
37
SIBMCLK
I/O
This pin is the master clock source for the SIB logic. This pin is available for use in one of two
modes. First, SIBMCLK can be configured as a high-rate output master clock source required by
certain external codec devices. In this mode all SIB clocks are synchronously slaved to the main
PR31500 system clock CLK2X. Conversely, SIBMCLK can be configured as an input slave clock
source. In this mode, all SIB clocks are derived from an external SIBMCLK oscillator source,
which is asynchronous with respect to CLK2X. Also, for this mode, SIBMCLK can still be
optionally used as a high-rate master clock source required by certain external codec devices.
SPI Pins
67
SPICLK
O
This pin is used to clock data in and out of the SPI slave device.
69
SPIOUT
O
This pin contains the data that is shifted into the SPI slave device.
68
SPIIN
I
This pin contains the data that is shifted out of the SPI slave device.
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