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參數(shù)資料
| 型號： | PR31500ABC |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Poseidon embedded processor |
| 中文描述： | RISC PROCESSOR, PQFP208 |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 277K |
| 代理商： | PR31500ABC |
Philips Semiconductors
Preliminary specification
MIPS
PR31500
Poseidon embedded processor
1996 Sep 24
4
OVERVIEW
Each of the on-chip peripherals consist of:
BIU Module
System memory and PR31500 Bus Interface Unit (BIU)
–
supports up to 2 banks of physical memory
–
supports self-refreshing DRAM and SDRAM
–
programmable parameters for each bank of DRAM or SDRAM
(row/column address configuration, refresh, burst modes, etc.)
programmable chip select memory access
–
4 programmable (size, wait states, burst mode control) memory
device and general purpose chip selects
available for system ROM, SRAM, Flash
available for external port expansion registers
supports up to 2 identical full PCMCIA ports
–
PR31500 and UCB1100 provide the control signals and accepts
the status signals which conform to the PCMCIA version 2.01
standard
–
appropriate connector keying and level-shifting buffers required
for 3.3V versus 5V PCMCIA interface implementations
SIU Module
multi-channel 32-bit DMA controller and System Interface Unit
(SIU)
independent DMA channels for video, SIB to/from UCB1100
audio/telecom codecs, high-speed serial port, IR UART, and
general purpose UART
address decoding for submodules within System Interface Module
(SIM)
CPU Module
R3000 RISC central processing unit core
–
full 32-bit operation (registers, instructions, addresses)
–
32 general purpose 32-bit registers; 32-bit program counter
–
MIPS RISC Instruction Set Architecture (ISA) supported
on-chip cache
–
4 KByte direct-mapped instruction cache (I-cache)
physical address tag and valid bit per cache line
programmable burst size
instruction streaming mode supported
–
1 KByte data cache (D-cache)
physical address tag and valid bit per cache line
programmable burst size
write-through
–
cache address snoop mode supported for DMA
–
4-level deep write buffer
Memory Management Unit
–
MIPS R3000A MMU contains on-chip TLB with:
32
×
64 bit wide entries
fully associative
2 entry micro TLB for very fast instruction address translation
Instruction address translation accesses full TLB after micro
TLB miss
Data address translation accesses full TLB
high-speed multiplier/accumulator
–
on-chip hardware multiplier
–
supports 16x16 or 32x32 multiplier operations, with 64-bit
accumulator
–
existing multiply instructions are enhanced and new multiply
and add instructions are added to R3000 instruction set to
improve the performance of DSP applications
CPU interface
–
handles data bus, address bus, and control interface between
CPU core and rest of PR31500 logic
Clock Module
PR31500 supports system-wide single crystal configuration,
besides the 32 KHz RTC XTAL (reduces cost, power, and board
space)
common crystal rate divided to generate clock for CPU, video,
sound, telecom, UARTs, etc.
external system crystal rate is vendor-dependent
independent enabling or disabling of individual clocks under
software control, for power management
CHI Module
high-speed serial Concentration Highway Interface (CHI) contains
logic for interfacing to external full-duplex serial
time-division-multiplexed (TDM) communication peripherals
supports ISDN line interface chips and other PCM/TDM serial
devices
CHI interface is programmable (number of channels, frame rate,
bit rate, etc.) to provide support for a variety of formats
supports data rates up to 4.096 Mbps
independent DMA support for CHI receive and transmit
Interrupt Module
contains logic for individually enabling, reading, and clearing all
PR31500 interrupt sources
interrupts generated from internal PR31500 modules or from edge
transitions on external signal pins
IO Module
contains support for reading and writing the 7 bi-directional
general purpose IO pins and the 32 bi-directional multi-function IO
pins
each IO port can generate a separate positive and negative edge
interrupt
independently configurable IO ports allow PR31500 to support a
flexible and wide range of system applications and configurations
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