MD622P是一種高速12位數(shù)字模擬轉(zhuǎn)換器(DAC)結(jié)合書(12渠道2:1)輸入多路復(fù)用器。轉(zhuǎn)換器可以操作在一個(gè)采樣率高達(dá)4.5Gsps時(shí)。數(shù)字?jǐn)?shù)據(jù)輸入與芯片上的LVDS 100歐姆電阻終止。后48對(duì)微分?jǐn)?shù)據(jù)輸入的多路復(fù)用的2倍速度,12高速數(shù)據(jù)位是閂鎖和編碼DAC輸出級(jí)。DAC的模擬輸出在正常握模式之間選擇(1日尼奎斯特樂隊(duì))或歸零模式(第一,第二和第三尼奎斯特樂隊(duì))操作?;パa(bǔ)輸出可用50-?輸出終端。Divided-by-4時(shí)鐘LVDS輸出和采樣階段選擇(SEL1和SEL2)提供緩解抽樣階段的定位相對(duì)于輸入數(shù)據(jù)。除以2鐘LVDS輸出還提供。重置功能為系統(tǒng)提供應(yīng)用程序需要從多個(gè)MD622P輸出的同步。
MD622P is a high-speed 12-bit Digital to Analog Converter (DAC) integrated with a 24:12 (12 channels of 2:1) input multiplexer. The converter can be operated at a sampling rate up to 4.5 Gsps. The digital data inputs are LVDS with on-chip 100 ohm termination resistors. After the 48 pairs of differential data inputs were multiplexed up to 2 times of speed, the 12 high speed data bits are latched and encoded to drive DAC output stage. The analog outputs of DAC can be selected between Normal-Hold mode (for the 1st Nyquist band ) or Return-to-Zero mode (for the 1st, 2nd and 3rd Nyquist band) operation. Complementary outputs are available with 50-? output back terminations. Divided-by-4 clock LVDS outputs and sampling phase selection (SEL1 and SEL2) are provided to ease the alignment of sampling phase relative to the input data. Divided-by-2 clock LVDS outputs are also provided. A RESET function is provided for system applICations which need to synchronize the outputs from multiple MD622P’s.
特性
12位DAC > 4-GSPS利率決議
DAC模擬輸出格式可以選擇之間正常握(NH)模式或歸零(RZ)模式
每個(gè)輸入2:1復(fù)用率DAC
SFDR比-50 dBc
輔以50-?輸出終端
互補(bǔ)除以2 LVDS輸出數(shù)據(jù)同步
變量400 ~ 800 mVPP單端輸出擺動(dòng)
芯片上的每個(gè)微分100歐姆之間終止
LVDS輸入數(shù)據(jù)和復(fù)位
QFN 10 x10 88 l包墊
單電源+ 5 v 2.3 W的權(quán)力消費(fèi)
應(yīng)用程序
生成任意波形
雷達(dá)/激光雷達(dá)設(shè)計(jì)和測(cè)試
軟件定義無(wú)線電
電子戰(zhàn)
無(wú)線基站
射頻信號(hào)源的一代
WLAN測(cè)試
高級(jí)通信調(diào)節(jié)
深圳市立維創(chuàng)展科技有限公司
雷麗芳 (銷售工程師)
電話:0755-8305-0846 1353-777-4422
QQ:1912856821
傳真:0755-83035176
地址:廣東省深圳市福田區(qū)車公廟泰然九路1號(hào)盛唐大廈西座702
網(wǎng)站:www.leadwaytk.com