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參數資料
| 型號： | PS2500 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | Low-Power Direct Digital Modulation Frequency Synthesizer |
| 中文描述： | 低功耗直接數字調制頻率合成器 |
| 文件頁數： | 20/28頁 |
| 文件大?。?/td> | 184K |
| 代理商： | PS2500 |
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PS2500 2.2 GHz Fractional-N Frequency Synthesizer
- 20 -
Philsar Semiconductor Inc.
146 Colonnade Road S.
Nepean, Ontario, Canada
K2E 7Y1
Tel: 613-274-0922
Fax: 613-274-0915
www.philsar.com
PMP-001-DS2 V1.2
This register contains the integer portion closest to the desired fractional-N (or the integer-N) value minus
32 for the main synthesizer. This register, in conjunction with the main dividend registers (which controls
the fraction offset from -0.5 to +0.5), permits selection of a precise frequency.
Values to be loaded are:
Main Synthesizer Divider Index
= 9-bit value for the integer portion of the main synthesizer dividers.
Valid values for this register are from 6 to 505 (fractional-N) or from 0 to 511 (integer-N).
Figure 5: Hex1
Main Dividend MSB Register
(Write only)
Figure 6: Hex2
Main
Dividend LSB
Register
(Write only)
These registers control the fraction part of the desired fractional-N value and permit an offset of - 0.5 to +
0.5 to the main integer selected through the Main Divider Register.
Values to be loaded are:
Main Synthesizer Dividend (MSBs)
= 10-bit value for the MSBs of the 18-bit dividend for the main
synthesizer.
Main Synthesizer Dividend (LSBs)
= 8-bit value for the LSBs of the 18-bit dividend for the main
synthesizer.
Note:
When in 10-bit mode, the
Main Synthesizer Dividend (LSBs)
is not required.
For information on programming these registers, see “Synthesizer Register Programming” on page 6. For
information on loading order for these registers, see “Register Loading Order” on page 9.
Main Synthesizer Dividend (MSBs)
A3
0
1
2
3
4
5
6
7
8
9
10
11
0
A0
A1
A2
0
0
1
X
X
Main Synthesizer Dividend (LSBs)
A3
0
1
2
3
4
5
6
7
8
9
10
11
0
A0
A1
A2
0
1
0
X
X
X
X
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