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PSD3XX – Application Note 022
1-202
The 80C31
Family
A number of 80C31 versions are offered from several suppliers that include different
functions on-chip, but versions such as the 80C32 have different internal memory sizes as
well. Each of these versions has retained the core architecture and external memory
access requirements of the basic 80C31.
The 80C51 family memory model is composed of two separate memory spaces or
allocations. Program space is intended for storage of the program control code (usually in
EPROM) and data space is intended for storage of temporary or changeable information
(usually in SRAM). Data space is also where most memory mapped I/O is located. In
external memory operation, the 80C31 uses the PSEN signal to access program memory
and the RD signal accesses the data memory. The PSD3XX's programmability provides for
this memory model (called "separate space") as well as other memory models.
Program and data space do not always need to be separated. In fact, most controller
architectures make no distinction between program and data space. If this memory model is
desired, the PSD3XX will internally OR the PSEN and RD signals together and EPROM,
SRAM and I/O will be available in the same memory space (called "combined space").
In "combined space", program code can be stored in EPROM or SRAM. This can be very
important if the user has program code that is downloaded into SRAM, or if the system
uses lookup table contents that depend on system parameters not known until the system is
operating. Anytime the program code needs to be easily changeable, SRAM is a
convenient way to store it. Figure 2 illustrates how the PSD3XX would be connected to the
80C31 and tables 1 and 2 convey some of the choices made via the PSD Development
System Software to configure the PSD3XX as "separate" or "combined" address space.
MICROCONTROLLER
31
19
18
9
12
13
14
15
1
2
3
4
5
6
7
8
23
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39
22
2
1
13
3
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
RD
WR
PSEN
ALE
TXD
RXD
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
A19/CSI
39
38
37
36
35
34
33
32
21
22
23
24
25
26
27
28
17
16
29
30
11
10
21
20
19
18
17
16
15
14
11
10
9
8
7
6
5
4
40
41
42
43
EA/VP
X1
X2
RESET
INT0
INT1
T0
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
AD0/A0
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
AD8/A8
AD9/A9
AD10/A10
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15
RD
WR/V
PP
BHE/PSEN
ALE
RESET
GND
PSD312
80C31
34
12
V
CC
44
0.1μF
Figure 2.
80C31/PSD312
Interface
Simplicity