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Introduction
Programmable Peripheral
Application Note 020
Benefits of 16-Bit Design with PSD3XX
By Ching Lee
Embedded controller architecture has been evolving from 4-bit, 8-bit to 16-bit through the
years. The increase in the data bus bandwidth is a natural progression for microcontrollers
to achieve higher performance. Today, 16-bit embedded controllers such as the 80C196 and
683XX families provide excellent performance at reasonable cost. Yet many designers are
weary of the cost of higher chip count, more board space and power consumption in 16-bit
applications and prefer to stay with 8-bit designs. Some microcontroller manufacturers
tackle this problem by introducing processors with 16-bit internal architectures but have 8-bit
external data busses. Later additional enhancements such as dynamic bus sizing provide
the choice of selecting either an 8 or 16-bit bus for further cost reduction. This compromise
certainly increases the performance; it is still not as good as a true 16-bit implementation.
With the introduction of the PSD3XX family of field programmable microcontroller peripher-
als from WSI, there is no reason not to use 16-bit microcontrollers. The PSD3XX provides
an integrated solution in a single chip, which includes user configurable I/O ports, Chip
Select outputs, logic replacement, Page Register, Programmable Address Decoder (PAD),
EPROM and SRAM. The PSD3XX is a perfect match for 16-bit microcontroller applications.
In this application note, we will look at some of the advantages of 16-bit designs, and how
PSD3XX interfaces to microcontrollers such as the 80C196 and 68302.
Typical 16-Bit
Microcontroller
System
Architecture
There is no one standard 16-bit architecture, especially in the field of embedded controller
applications. For a typical 80C196 design, the basic building block consists of two address
latches (74AC373), address decoding logic (with PAL or discrete logic), program memory
(EPROMs), data memory (one or more SRAM), and I/O devices.
Figure 1 is the schematic of such a system. In this design, 64K bytes of program
memory/EPROM, and a 2K byte SRAM for scratch pad are required. Since the 80C196 has
only 64K byte memory space, the INST signal provides the paging capability, with program
memory residing in the first 64K page while SRAM and I/O devices occupy the second
page. The I/O section consists of one output port (74AC374) and other peripheral devices.
The chip select signals for the I/O devices and memory are connected directly from the
decoding PAL outputs. The processor’s data bus width is determined by the type of bus
cycle. EPROM accesses are 16-bits wide, SRAM is 8-bits while I/O bus cycles can be 8 or
16-bits, depending on the device being accessed. The BWIDTH output from the PAL
informs the processor what type of bus width is to be expected for that particular cycle.
An I/O device usually takes longer time to complete the bus cycle. Let us assume, in this
case, I/O devices require 3 wait states with the exception of the I/O latch. The configuration
register of the 80C196 is then programmed to insert 3 wait states. Whenever there is an I/O
bus cycle, the READY output signal from the PAL goes low to activate the processor’s wait
state control to insert the programmed amount of wait state. For memory bus cycles, no
wait state is inserted.
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