參數(shù)資料
型號(hào): PSD311R
英文描述: Field Programmable Microcontroller Peripherals(可編程邏輯,無(wú)SRAM,19個(gè)可編程I/O,通用PLD有12個(gè)輸入)
中文描述: 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備(可編程邏輯,無(wú)的SRAM,19余個(gè)可編程輸入/輸出,通用PLD的有12個(gè)輸入)
文件頁(yè)數(shù): 61/127頁(yè)
文件大小: 682K
代理商: PSD311R
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PSD3XX Famly
2-61
Figure 38.
Port A as
AD0–AD7 Timng
(Track Mode),
CRRWR = 1
(PSD3X2/3X3/3X4R)
33
25
33
32
12
28
24
34
35
DATA VALID
12
1
32
32
23
24
26
2
ADDRESS
ADDRESS
2
3
2
35
READ CYCLE
WRITE CYCLE
STABLE INPUT
STABLE INPUT
STABLE INPUT
STABLE INPUT
Direct
PAD Input
(48,51)
Multiplexed
PAD Inputs
(52,54)
A0/AD0-
A7/AD7
or AS
AS
RD/E/DS as E
WR/V
PP
or
R/W as R/W
1
3
34
27
23
RD/E/DS as DS
PA0-PA7
29
CSOi
(50,53)
ADR OUT
DATA IN
DATA
OUT
WRITTEN
DATA
ADR OUT
48. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19,
RD/E/DS, WR or R/W, transparent PC0–PC2, ALE in non-multiplexed modes.
49. Multiplexed inputs: any of the following inputs that are latched by the ALE (or AS):
A0/AD0–A15/AD15, CSI/A19 as ALE dependent A19, ALE dependent PC0–PC2.
50. CSOi = any of the chip-select output signals coming through Port B (CS0–CS7) or through
Port C (CS8–CS10).
51. CSADOUT1, which internally enables the address transfer to Port A, should be derived only
from direct PAD input signals, otherwise the address propagation delay is slowed down.
52. CSADIN and CSADOUT2, which internally enable the data-in or data-out transfers, respectively,
can be derived from any combination of direct PAD inputs and multiplexed PAD inputs.
53. The write operation signals are included in the CSOi expression.
54. Multiplexed PAD inputs: any of the following PAD inputs that are latched by the ALE (or AS) in
the multiplexed modes: A11/AD11–A15/AD15, CSI/A19 as ALE dependent A19, ALE dependent
PC0–PC2.
55. CSOi product terms can include any of the PAD input signals shown in Figure 3, except for reset
and CSI.
Notes for
Timng
Dagrams
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