參數(shù)資料
型號： PSD313L
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,19個可編程I/O,通用PLD有16個輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設備（可編程邏輯，16K的位的SRAM，19余個可編程輸入/輸出，通用PLD的有16個輸入）
文件頁數(shù)： 11/127頁
文件大小： 682K
代理商： PSD313L
PSD3XX Famly
2-11
Programmable
Address
Decoder (PAD)
The PSD3XX consists of two programmable arrays referred to as PAD A and PAD B
(Figure 3). PAD A is used to generate chip select signals derived from the input address to
the internal EPROM blocks, SRAM, I/O ports, and Track Mode signals. All its I/O functions
are listed in Table 3 and shown in Figure 3. PAD B outputs to Ports B and C for off-chip
usage.
PAD B can also be used to extend the decoding to select external devices or as a random
logic replacement. The input bus to both PAD A and PAD B is the same. By using the
PSDsoft Development Tools software, each programmable bit in the PAD array can have
one of three logic states of 0, 1, and don’t care (X). In a user’s logic design, both PADs can
share the same inputs, using the X for input signals that are not supposed to affect other
functions. The PADs use reprogrammable CMOS EPROM technology and can be
programmed and erased (if using windowed packages) by the user.
Multiplexed Address/Data
Non-Multiplexed Address/Data
8-bit Data Bus
I/O or low-order address
lines or low-order multiplexed
address/data byte
Port A
D0–D7 data bus byte
Port B
I/O and/or CS0–CS7
I/O and/or CS0–CS7
AD0/A0–AD7/A7
Low-order multiplexed
address/data byte
Low-order address bus byte
AD8/A8–AD15/A15
High-order multiplexed
address data byte
High-order address bus byte
16-bit Data Bus
I/O or low-order address
lines or low-order multiplexed
address/data byte
Port A
Low-order data bus byte
Port B
I/O and/or CS0–CS7
High-order data bus byte
AD0/A0–AD7/A7
Low-order multiplexed
address/data byte
Low-order address bus byte
AD8/A8–AD15/A15
High-order multiplexed
address/data byte
High-order address bus byte
Table 2.
PSD30X Bus
and Port
Configuration
Options
Multiplexed Address/Data
Non-Multiplexed Address/Data
8-bit Data Bus
I/O or low-order address
lines or low-order multiplexed
address/data byte
Port A
D0–D7 data bus byte
Port B
I/O and/or CS0–CS7
I/O and/or CS0–CS7
AD0/A0–AD7/A7
Low-order multiplexed
address/data byte
Low-order address bus byte
A8–A15
High-order address bus byte
High-order address bus byte
Table 2a.
PSD31X Bus
and Port
Configuration
Options
相關PDF資料
PDF描述
PSD314RL Field Programmable Microcontroller Peripherals(可編程邏輯,無SRAM,19個可編程I/O,通用PLD有16個輸入)
PSD301 Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,19個可編程I/O,通用PLD有12個輸入)
PSD302 Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,19個可編程I/O,通用PLD有16個輸入)
PSD313 Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,19個可編程I/O,通用PLD有16個輸入)
PSD3A011-01 Interface IC
相關代理商/技術參數(shù)
參數(shù)描述
PSD313L-15J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD313L-15JI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD313L-15LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD313L-15LM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD313L-15U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*