參數(shù)資料
型號: PSD313R
英文描述: Field Programmable Microcontroller Peripherals(可編程邏輯,無SRAM,19個可編程I/O,通用PLD有16個輸入)
中文描述: 現(xiàn)場可編程微控制器外圍設(shè)備(可編程邏輯,無的SRAM,19余個可編程輸入/輸出,通用PLD的有16個輸入)
文件頁數(shù): 1/127頁
文件大小: 682K
代理商: PSD313R
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Single Chip Programmable Peripheral for Microcontroller-based Applications
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Wide Operating Voltage Range
— L-Versions: 3.0 to 5.5 volts
— Others: 4.5 to 5.5 volts
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19 Individually Configurable I/O pins that can be used as
— Microcontroller I/O port expansion
— Programmable Address Decoder (PAD) I/O
— Latched address output
— Open drain or CMOS
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Two Programmable Arrays (PAD A and PAD B)
— Total of 40 Product Terms and up to 16 Inputs and 24 Outputs
— Address Decoding up to 1 MB
— Logic replacement of discrete PALs
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“No Glue” Microcontroller Chip-Set
— Built-in address latches for multiplexed address/data bus
— Non-multiplexed address/data bus mode
— ALE and Reset (non-PSD3XXL versions) polarity programmable
— Selectable modes for read and write control bus as RD/WR or R/W/E
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256K to 2 MBits of UV EPROM (2 Mbit version is SRAMless)
— Configurable as 32, 64, 128 or 256K x 8 or as 16, 32, 64 or 128K x 16
— Divides into 8 equal mappable blocks for optimized mapping
— Block resolution is 4K x 8 or 2K x 16 (PSD3X1) to 32K x 8 or 16K x 16 (PSD3X4R)
— As fast as 70 ns EPROM access time, including input latches and
PAD address decoding.
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16 Kbit Static RAM (No SRAM on PSD3XXR versions)
— Configurable as 2K x 8 or as 1K x 16
— As fast as 70 ns SRAM access time, including input latches and PAD address decoding
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Built-in Page Logic (PSD3X2/3X3/3X4R)
— Expands the MCU address space up to sixteen 1 Mb pages
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CMiser Bit
— Programmable option to further reduce power consumption
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Address/Data Track Mode
— Enables easy Interface to Shared Resources (Mail Box SRAM) with other
Microcontrollers or a Host Processor
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Built-In Security
— Locks the device and PAD Decoding configuration
Key Features
Programmable Peripheral
PSD3XX Famly
Field-Programmable Microcontroller Peripheral
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PSD302L Field Programmable Microcontroller Peripherals(可編程邏輯,16K位SRAM,19個可編程I/O,通用PLD有16個輸入)
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