參數(shù)資料
型號: PSD402A1-15J
英文描述: Hi-Rel Adjustable Voltage 3-Terminal Positive Regulator; Qualified Part Number similar to OM1321NKM
中文描述: 現(xiàn)場可編程外圍
文件頁數(shù): 89/123頁
文件大小: 657K
代理商: PSD402A1-15J
PSD4XX Famly
86
-70
-90**
-15
ZPLD_TURBO
OFF
*
Symbol
Parameter
Conditions
Min
Max
Min Max
Min Max
Unit
t
AVQV (PA)
Address Valid to
Data Valid
(Note 3)
45
55
62
Add 10
ns
t
SLQV (PA)
CS Valid to Data
Valid
55
55
62
Add 10
ns
RD to Data Valid
RD to Data Valid
8031 Mode
Data In to Data Out
Valid
(Notes 1 and 4)
22
26
45
0
ns
t
RLQV (PA)
32
38
45
0
ns
t
DVQV (PA)
22
22
26
0
ns
t
QXRH (PA)
t
RLRH (PA)
t
RHQZ (PA)
RD Data Hold Time
(Note 1)
0
0
0
0
ns
RD Pulse Width
(Note 1)
25
30
38
0
ns
RD to Data High-Z
(Note 1)
20
25
33
0
ns
Port A Peripheral Data Mode Read Timng
(5 V ± 10%)
-70
-90**
-15
ZPLD_TURBO
OFF
Symbol
Parameter
Conditions
Min
Max
Min Max
Min
Max
Unit
t
WLQV (PA)
WR to Data
Propagation Delay
(Note 2)
25
27
35
0
ns
t
DVQV (PA)
Data to Port A Data
Propagation Delay
(Note 5)
22
22
26
0
ns
t
WHQZ (PA)
WR Invalid to
Port A Tri-state
(Note 2)
20
25
33
ns
Port A Peripheral Data Mode Write Timng
(5 V ± 10%)
NOTES:
1.
RD timing has the same timing as PSEN, DS, LDS, UDS signals.
WR timing has the same timing as E, DS, LDS, UDS, WRL, WRH signals.
Any input used to select Port A Data Peripheral Mode.
Data is already stable on Port A.
Data stable on ADIO pins to data on Port A.
2.
3.
4.
5.
*
*
If ZPLD_TURBO is off and the ZPLD is operating above 15 MHz, there is no need to add 10 ns to the timing parameters.
**
The -90 speed is available only on Industrial Temperature Range product.
Microcontroller Interface – AC/DC Parameters
(5 V ± 10% Versions)
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