參數資料
型號： PSD402A1-15U
英文描述： Hi-Rel Adjustable Voltage 3-Terminal Negative Regulator; Qualified Part Number similar to OM1322SMM
中文描述： 現場可編程外圍
文件頁數： 51/123頁
文件大?。?/td> 657K
代理商： PSD402A1-15U
PSD4XX Famly
48
9.3 I/OPorts
There are 5 programmable 8-bit I/O ports: Port A, Port B, Port C, Port D and Port E. These
ports all have multiple operating modes, depending on the configuration. Some of the basic
functions are providing input/output for the ZPLD, or can be used for standard I/O. Each
port pin is individually configurable, thus enabling a single 8-bit port to perform multiple
functions. The I/O ports occupy 256 bytes of memory space as defined by “CSIOP”. Refer
to the System Configuration section for I/O register address offset.
To set up the port configuration the user is required to:
1. Define I/O Port Chip Select (CSIOP) in the ABEL file.
2. Initialize certain port configuration registers in the user’s program and/or
3. Specify the configuration in the PSD4XX PSDsoft Software.
4. Unused input pins should be tied to V
CC
or GND.
The following is a description of the operating modes of the I/O ports. The functions of the
port registers are described in later sections.
9.3.1 Standard MCUI/O
The Standard MCU I/O Mode provides additional I/O capability to the microcontroller. In this
mode, the ports can perform standard I/O functions such as sensing or controlling various
external I/O devices. Operation options of this mode are as follows:
J
Configuration
1.Declare pins or signals which are used as I/O in the ABEL file.
2.Set the bit or bits in the Control Register to "1".
3.
As Output Port
– Write output data to Data Out Register
– Set Direction Register to output mode
4.
As Input Port
– Set Direction Register to input mode
– Read input from Data In Register
The port remains an output or input port as long as the Direction Register is not changed.
9.3.2 PLDI/O
The PLD I/O mode enables the port to be configured as an input to the ZPLD, or as an
output from the GPLD macrocell. The output can be tri-stated with a control signal defined
by a product term from the ZPLD. This mode is configured by the user in the PSD4XX
PSDsoft Software, and is enabled upon power up. For a detailed description, see the
section on the ZPLD.
J
Configuration
1.Declare pins or signals in the ABEL file (PSDsoft).
2.Write logic equations in the ABEL file.
3.PSD Compiler maps the PLD functions to the PSD.
The PSD4XX
Architecture
(cont.)
相關PDF資料
PDF描述
PSD402A1-15UI Hi-Rel Adjustable Voltage 3-Terminal Negative Regulator; A OM1322SMM with Standard Packaging
PSD402A1-20J Field-Programmable Peripheral
PSD402A1-20JI 30V Hi-Rel Synchronous Rectifier N-Channel MOSFET in a SMD-2 package; A IRHSNA57Z60 with Standard Packaging
PSD402A1-20LI -100V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a 18-pin LCC package; Similar to IRHE9130 with optional Total Dose Rating of 300kRads
PSD402A1-20LM Field-Programmable Peripheral
相關代理商/技術參數
參數描述
PSD402A1-15UI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD402A1-20J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD402A1-20JI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD402A1-20LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD402A1-20LM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
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