參數(shù)資料
型號: PSD402A1-20UI
英文描述: 100V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; Similar to IRHNA7160 with optional Total Dose Rating of 500kRads
中文描述: 現(xiàn)場可編程外圍
文件頁數(shù): 87/123頁
文件大小: 657K
代理商: PSD402A1-20UI
PSD4XX Famly
84
Explanation of AC Symbols for Non ZPLD Timing.
Example:
t
AVLX
Time from Address Valid to ALE Invalid.
A
– Address
C
– Power Down
D
– Input Data
E
– E
H
– Logic Level High
I
– Interrupt
L
– Logic Level Low or ALE
N
– Reset
P
– Port Signal
Q
– Output Data
R
– WR, UDS, LDS, DS, IORD, PSEN
S
– Chip Select
T
– R/W
t
– Time
V
– Valid
X
– No Longer a Valid Logic Level
Z
– Float
-70
-90*
-15
EPROM_CMiser
ON
Symbol
Parameter
Conditions
Min Max Min Max Min Max
Unit
t
LVLX
t
AVLX
t
LXAX
t
AVQV
ALE or AS Pulse Width
Address Setup Time
Address Hold Time
Address Valid to Data
Valid
CS Valid to Data Valid
RD to Data Valid
8/16-Bit Bus
RD to Data Valid 8-Bit
Bus, 8031 Separate
Mode
RD Data Hold Time
RD Pulse Width
RD to Data High-Z
E Pulse Width
R/W Setup Time
to Enable
R/W Hold Time After
Enable
18
5
7
20
6
8
28
10
11
0
0
0
ns
ns
ns
(Note 3)
(Note 3)
(Note 3)
70
90
150
Add 10
ns
t
SLQV
80
100
150
Add 10
ns
(Note 1)
20
32
40
0
ns
t
RLQV
(Note 2)
32
38
45
0
ns
t
RHQX
t
RLRH
t
RHQZ
t
EHEL
t
THEH
(Note 1)
(Note 1)
(Note 1)
0
0
0
0
0
0
0
ns
ns
ns
ns
30
32
38
22
25
33
30
32
38
8
10
18
0
ns
t
ELTL
0
0
0
0
ns
In 16-Bit Data Bus
Mode (Note 9)
In 8-Bit Data Bus
Mode (Note 9)
20
30
38
0
ns
t
AVPV
Address Input Valid to
Address Output Delay
22
32
48
0
ns
Read Timng
(5 V ± 10% Versions)
NOTES:
1.
RD timing has the same timing as PSEN, DS, LDS, UDS signals.
RD and PSEN have the same timing for 8031 mode.
Any input used to select an internal PSD4XX function.
In multiplexed mode latched address generated from ADIO delay to address output on any Port.
2.
3.
4.
*
The -90 speed is available only on Industrial Temperature Range product.
13.8 Microcontroller Interface – AC/DC Parameters
(5 V ± 10% Versions)
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