參數(shù)資料
型號(hào)： PSD403A1-70U
英文描述： -30V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a Low-Ohmic TO-257AA package; A IRHYB597Z30CM with Standard Packaging
中文描述： 現(xiàn)場(chǎng)可編程外圍
文件頁數(shù)： 79/123頁
文件大?。?/td> 657K
代理商： PSD403A1-70U
Port Configuration
Reset
Stand-by Mode
Port I/O
Input
Unchanged
ZPLD Output
Active
Depend on Inputs to the ZPLD
Address Out
Tri-stated
Not Defined
Data Port
Tri-stated
Tri-stated
Peripheral I/O
Tri-stated
Tri-stated
PSD4XX Famly
76
Register Name
Device
Reset State
Control
Port A, B, C, D, E
Set to “0”
(Address Out Mode)
Data Out
(data or address)
Port A, B, C, D, E
Set to “0”
Direction
Port A, B, C, D, E
Set to “0” – Input Mode
Open Drain
Port C, D
Set to “0” – CMOS Outputs
Page Register
Page Logic
Set to “0”
PMMR0, PMMR1
Power Management Unit
Set to “0”
VM
Volatile Memory
Set to “0”
System
Configuration
(cont.)
Table 24. Registers Reset Values
Table 25. I/OPin Status During Reset and Standby Mode
12.1 Reset Input
The reset input to the PSD4XX (RESET) is an active low signal which resets some of the
internal devices and configuration registers. The Timing Diagram in the AC/DC
characterization section shows the reset signal timing requirement. The active low range
has a minimum T1 duration. After the rising edge of RESET, the PSD4XX remains in
reset during T2 range. (See Figure 48). The PSD4XX must be reset at power up before it
can be used.
12.2 ZPLDand Memory During Reset
While the Reset Input is active, the ZPLD generates outputs as defined in the PSDabel
equations. The EPROM and SRAM blocks respond to the microcontroller bus cycle during
reset, but the data is not guaranteed.
12.3 Register Values During and After Reset
Table 24 summarizes the status of the volatile register values during and after reset.
The default values of the volatile registers are “0” after reset.
12.4 ZPLDMacrocell Initialization
The D flip flops in the macrocells in the GPLD can be cleared by:
J
A product term (.RE) defined by the user in PSDabel, or
J
The MACRO-RST (Reset) input, enabled and defined in PSDabel.
相關(guān)PDF資料
PDF描述
PSD403A1-90J 100V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package. Also available in 300kRad.; A IRHNA67160 with Standard Packaging
PSD403A1-90U 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a Low-Ohmic TO-257AA package. Also available with Total Dose Rating of 300kRads.; A IRHYS67230CM with Standard Packaging
PSD403A2 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a 18-pin LCC package; Similar to IRHE7230 with optional Total Dose Rating of 300kRads
PSD403A2-12J 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a 18-pin LCC package; A IRHE7230 with Standard Packaging
PSD403A2-12JI 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a 18-pin LCC package; Similar to IRHE7230 with optional Total Dose Rating of 1000kRads
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD403A1-90J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD403A1-90U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD403A1-C-15J 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals
PSD403A1-C-15L 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals
PSD403A1-C-15U 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals
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