參數(shù)資料
型號： PSD411A1-15LI
英文描述： -60V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a SMD-0.5 package; Similar to IRHNJ597034 with optional Total Dose Rating of 300kRads
中文描述： 現(xiàn)場可編程外圍
文件頁數(shù)： 74/123頁
文件大?。?/td> 657K
代理商： PSD411A1-15LI
PSD4XX Famly
71
The PSD4XX
Architecture
(cont.)
Port Configuration
Pin Status
I/O Port
Unchanged
ZPLD Output
Depend on Inputs to the ZPLD
Address Out
Undefined
Data Port
Tri-stated
Peripheral I/O
Tri-stated
Table 20. I/OPin Status During Power Down And Sleep Mode
J
Input Clock
The PSD4XX provides the option to turn off the clock inputs to save AC power
consumption. The clock input (CLKIN) is used as a source for driving the following
modules:
J
ZPLD Array Clock Input
J
ZPLD MacroCell Clock Flip Flop
J
APD Counter Clock
During power down or if any of the modules are not being used the clock to these
modules should be disabled. To reduce AC power consumption, it is especially
important to disable the clock input to the ZPLD array if it is not used as part of a logic
equation.
The ZPLD Array Clock can be disabled by setting PMMR0 bit 5 (ZPLD ACLK).
The ZPLD MacroCell Clock Input can be disabled by setting PMMR0 bit 6
(ZPLD RCLK). The Timer Clock can be disabled by setting PMMR0 bit 7
(TMR CLK). The APD Counter Clock will be disabled automatically if Power Down or
Sleep Mode is entered through the APD unit. The input buffer of the CLKIN input will be
disabled if bits 5 – 7 PMMR0 are set and the APD has overflowed.
PLD
PLD
Access
Time
Access
Recovery
Time To
Normal
Access
Propagation
Delay
Recovery
Time To
Normal
Operation
Power Down
Normal t
PD
(Note 1)
0
No Access
t
LVDV
Sleep
t
LVDV2
(Note 2)
t
LVDV3
(Note 3)
No Access
t
LVDV1
Summary of PSD4XX Timng and Standby Current During Power Down
and Sleep Modes
NOTES: 1. Power Down does not affect the operation of the ZPLD. The ZPLD operation in this mode is based
only on the ZPLD_Turbo Bit.
2. In Sleep Mode any input to the ZPLD will have a propagation delay of t
LVDV2
.
3. PLD recovery time to normal operation after exiting Sleep Mode. An input to the ZPLD during the
transition will have a propagation delay time of t
LVDV3
.
相關(guān)PDF資料
PDF描述
PSD411A1-15U 400V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a TO-205AF package; A IRHF7310SE with Standard Packaging
PSD411A1-15UI 250V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a TO-205AF package; JANS Certified Part Number
PSD411A1-20J 250V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a SMD-2 package; JANS Certified device. Equivalent to IR Part Number IRHNA57264SE
PSD411A1-20JI -30V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a SMD-2 package; A IRHNA597Z60 with Standard Packaging
PSD411A1-20LI 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a Low-Ohmic TO-257AA package; Similar to IRHYB67230CM with optional Total Dose Rating of 300kRads
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD411A1-15U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD411A1-15UI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD411A1-20J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD411A1-20JI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD411A1-20LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
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