- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368150 > PSD412A1-20UI -30V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a SMD-0.5 package; A IRHNJ597Z30 with Standard Packaging PDF資料下載
參數(shù)資料
| 型號： | PSD412A1-20UI |
| 英文描述： | -30V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a SMD-0.5 package; A IRHNJ597Z30 with Standard Packaging |
| 中文描述： | 現(xiàn)場可編程外圍 |
| 文件頁數(shù)： | 13/123頁 |
| 文件大小： | 657K |
| 代理商： | PSD412A1-20UI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁
PSD4XX Famly
10
9.0
The PSD4XX
Architecture
PSD4XX consists of five major functional blocks:
J
ZPLDBlocks
J
Bus Interface
J
I/OPorts
J
Memory Block
J
Power Management Unit
The functions of each block are described in the following sections. Many of the blocks
perform multiple functions, and are user configurable. The chip configurations are specified
by the user in the PSDsoft Development Software. Other configurations are specified by
setting up the appropriate bits in the configuration registers during run time.
9.1 The ZPLDBlock
The PSD4XX series devices provide two ZPLD configurations. The ZPLD in the
PSD4XXA1
devices has 8 registered macrocells, 8 combinatorial macrocells, and up to 113
product terms.
The
PSD4XXA2
has a full function ZPLD with 24 registered macrocells and up to 126
product terms.
9.1.1 The PSD4XXA1 ZPLDBlock
Key Features
J
2 Embedded ZPLD devices
J
8 registered and 8 combinatorial macrocells
J
Combinatorial/registered outputs
J
Maximum 113 product terms
J
Programmable output polarity
J
User configured register clear/preset
J
User configured register clock input
J
37 Inputs
J
Accessible via 16 I/O pins
J
Power Saving Mode
J
UV-Erasable
General Description
The ZPLD block has 2 embedded PLD devices:
J
DPLD
The Address Decoding PLD, generating select signals to internal I/O or memory blocks.
J
GPLD
The General Purpose PLD provides 8 registered and combinatorial programmable
macrocells for general or complex logic implementation; dedicated to user application.
Figure 4 shows the architecture of the ZPLD. The PLD devices all share the same input
bus. The true or complement of the 37 input signals are fed to the programmable
AND-ARRAY. Names and sources of the input signals are shown in Table 3. The PB
signals, depending on user configuration, can either be macrocell feedbacks or inputs from
Port B.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD412A1-70J | -100V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a TO-205AF package; A IRHF597130 with Standard Packaging |
| PSD412A1-70U | -30V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a Low-Ohmic TO-254AA package; A IRHMS597Z60 with Standard Packaging |
| PSD412A1-90J | Field-Programmable Peripheral |
| PSD412A1-90U | 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-1 package; A IRHN7230 with Standard Packaging |
| PSD412A2 | 100V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a 18-pin LCC package; Similar to IRHE7130 with optional Total Dose Rating of 300kRads |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD412A1-70J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD412A1-70U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD412A1-90J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD412A1-90U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral |
| PSD412A1-A-20JI | 制造商:WSI 功能描述:PERIPHERAL IC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。