參數(shù)資料
型號(hào): PSD413A1-20LM
英文描述: -100V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a SMD-0.5 package; Similar to IRHNJ9130 with optional Total Dose Rating of 300kRads
中文描述: 現(xiàn)場(chǎng)可編程外圍
文件頁(yè)數(shù): 68/123頁(yè)
文件大?。?/td> 657K
代理商: PSD413A1-20LM
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PSD4XX Famly
65
The PSD4XX
Architecture
(cont.)
Figure 34. Port A In Peripheral I/OMode
RD
PSEL0
PSEL1
D0 – D7
WR
PA0 – PA7
9.4.5 Peripheral I/O
The Peripheral I/O Mode is one of the operating modes of Port A. In this mode, Port A
is connected to the data bus of peripheral devices. Port A is enabled only when
the microcontroller is accessing the devices, otherwise the Port is tri-stated. This feature
enables the microcontroller to access external devices without requiring buffers and
decoders. Figure 34 shows the structure of Port A in the Peripheral I/O Mode.
The memory address space occupied by the devices are defined by two signals: PSEL0
and PSEL1. The signals are direct outputs from the Decoding PLD (DPLD). Whenever any
of the signals is active, the Port A driver is enabled, and the direction of the data flow is
determined by the RD/WR signals.
The Peripheral I/O Mode and the peripheral select signals are configured and defined in the
PSDsoft Software (see the section on I/O Port for configuration). The PIO bit in the VM
Register (see Table 17) also needs to be set to “1” by the user to initialize the Peripheral I/O
Mode.
The Peripheral I/O mode can be used, for example, in DMA applications where the
microcontroller does not support DMA operations, such as tri-stating the address/data bus.
Figure 35 shows a block diagram of a microcontroller and PSD4XX based design that
makes use of this mode. In this application, the microcontroller has a multiplexed bus which
is connected to the ADIO port. The C and D ports connect to the peripheral address bus
and are both configured in Address Out Mode. Port A is configured in the Peripheral I/O
mode and is connected to the peripheral data bus. Ports B and E are used to generate
control signals.
During normal activity, the microcontroller has access to any peripheral (memory or I/O
device) through the PSD4XX device. When there is a DMA request, the
microcontroller tri-states the address bus on Ports C and D by writing a “0” to the port
Direction Registers. The DMA controller then takes over the data and address buses after
receiving acknowledgement from the microcontroller.
相關(guān)PDF資料
PDF描述
PSD413A1-20U -60V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a Low-Ohmic TO-257AA package; Similar to IRHYS597034CM with optional Total Dose Rating of 300kRads
PSD413A1-20UI -100V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a TO-204AA package; A IRH9130 with Standard Packaging
PSD413A1-70J Field-Programmable Peripheral
PSD413A1-70U 60V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a TO-257AA Low-Ohmic Tabless package; A IRHYB597034CM with Standard Packaging
PSD413A1-90J 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-0.5 package; Similar to IRHNJ57230 with optional Total Dose Rating of 500kRads
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