參數(shù)資料
型號： PSD413A1-20LM
英文描述： -100V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a SMD-0.5 package; Similar to IRHNJ9130 with optional Total Dose Rating of 300kRads
中文描述： 現(xiàn)場可編程外圍
文件頁數(shù)： 79/123頁
文件大小： 657K
代理商： PSD413A1-20LM
Port Configuration
Reset
Stand-by Mode
Port I/O
Input
Unchanged
ZPLD Output
Active
Depend on Inputs to the ZPLD
Address Out
Tri-stated
Not Defined
Data Port
Tri-stated
Tri-stated
Peripheral I/O
Tri-stated
Tri-stated
PSD4XX Famly
76
Register Name
Device
Reset State
Control
Port A, B, C, D, E
Set to “0”
(Address Out Mode)
Data Out
(data or address)
Port A, B, C, D, E
Set to “0”
Direction
Port A, B, C, D, E
Set to “0” – Input Mode
Open Drain
Port C, D
Set to “0” – CMOS Outputs
Page Register
Page Logic
Set to “0”
PMMR0, PMMR1
Power Management Unit
Set to “0”
VM
Volatile Memory
Set to “0”
System
Configuration
(cont.)
Table 24. Registers Reset Values
Table 25. I/OPin Status During Reset and Standby Mode
12.1 Reset Input
The reset input to the PSD4XX (RESET) is an active low signal which resets some of the
internal devices and configuration registers. The Timing Diagram in the AC/DC
characterization section shows the reset signal timing requirement. The active low range
has a minimum T1 duration. After the rising edge of RESET, the PSD4XX remains in
reset during T2 range. (See Figure 48). The PSD4XX must be reset at power up before it
can be used.
12.2 ZPLDand Memory During Reset
While the Reset Input is active, the ZPLD generates outputs as defined in the PSDabel
equations. The EPROM and SRAM blocks respond to the microcontroller bus cycle during
reset, but the data is not guaranteed.
12.3 Register Values During and After Reset
Table 24 summarizes the status of the volatile register values during and after reset.
The default values of the volatile registers are “0” after reset.
12.4 ZPLDMacrocell Initialization
The D flip flops in the macrocells in the GPLD can be cleared by:
J
A product term (.RE) defined by the user in PSDabel, or
J
The MACRO-RST (Reset) input, enabled and defined in PSDabel.
相關(guān)PDF資料
PDF描述
PSD413A1-20U -60V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a Low-Ohmic TO-257AA package; Similar to IRHYS597034CM with optional Total Dose Rating of 300kRads
PSD413A1-20UI -100V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a TO-204AA package; A IRH9130 with Standard Packaging
PSD413A1-70J Field-Programmable Peripheral
PSD413A1-70U 60V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a TO-257AA Low-Ohmic Tabless package; A IRHYB597034CM with Standard Packaging
PSD413A1-90J 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-0.5 package; Similar to IRHNJ57230 with optional Total Dose Rating of 500kRads
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD413A2-C-70L 制造商:WSI 功能描述:
PSD4-16 制造商:Tamura Corporation of America 功能描述:
PSD4-20 制造商:MICROTRAN 功能描述:POWER TRANSFORMER, 6 VA
PSD4235G2-70U 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD4235G2-90U 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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