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| 型號： | PSD413F |
| 英文描述： | Field Programmable Microcontroller Peripherals with Flash Memory(可編程邏輯，16K位SRAM,35個(gè)可編程I/O,通用PLD有59個(gè)輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備與快閃記憶體（可編程邏輯，16K的位的SRAM，35余個(gè)可編程輸入/輸出，通用PLD的有59個(gè)輸入） |
| 文件頁數(shù)： | 91/98頁 |
| 文件大小： | 365K |
| 代理商： | PSD413F |
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PSD413F Family
6-91
ADVANCE INFORMATION
Write
Operation
Status
DQ7
Data Polling
The Flash memory features Data Polling as a method to indicate to the host that the
embedded algorithms are in progress or completed. During the Embedded Program
Algorithm, an attempt to read the device will produce the complement of the data last
written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read
the device will produce the true data last written to DQ7. During the Embedded Erase
Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon
completion of the Embedded Erase Algorithm an attempt to read the device will produce a
“1” at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in Figure 3.
For chip erase, the Data Polling is valid after the rising edge of the sixth WRF pulse in the
six write pulse sequence. For sector erase, the Data Polling is valid after the last rising edge
of the sector erase WRF pulse. Data Polling must be performed at sector addresses within
any of the sectors being erased and
not
a sector that is protected. Otherwise, the status
may not be valid.
Just prior to the completion of Embedded Algorithm operations DQ7 may change
asynchronously while the output enable (RDF) is asserted low. This means that the device
is driving status information on DQ7 at one instant of time and then that byte’s valid data at
the next instant of time. Depending on when the system samples the DQ7 output, it may
read the status or valid data. Even if the device has completed the Embedded Algorithm
operations and DQ7 has a valid data, the data outputs on DQ0 – DQ6 may be still invalid.
The valid data on DQ0 – DQ7 can be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm,
Embedded Erase Algorithm or sector erase time-out (see Table 4).
DQ6
Toggle Bit
The Flash memory also features the “Toggle Bit” as a method to indicate to the host system
that the embedded algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read
(RDF toggling) data from the device at any address will result in DQ6 toggling between one
and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6
will stop toggling and valid data will be read on the next successive attempt. During
programming, the Toggle Bit is valid after the rising edge of the fourth WRF pulse in the four
write pulse sequence. For chip erase, the Toggle Bit is valid after the rising edge of the sixth
WRF pulse in the six write pulse sequence. For Sector erase, the Toggle Bit is valid after
the last rising edge of the sector erase WRF pulse. The Toggle Bit is active during the
sector erase time-out.
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal
pulse count). Under these conditions DQ5 will produce a “1”. This is a failure condition
which indicates that the program or erase cycle was not successfully completed. Data
Polling is the only operating function of the device under this condition. The CSF circuit will
partially power down the device under these conditions (to approximately 2 mA). The RDF
and WRF pins will control the output disable functions.
The DQ5 failure condition will also appear if a user tries to program a “1” to a location that is
previously programmed to “0”. In this case the device locks out and never completes the
Embedded Program Algorithm. Hence, the system never reads a valid data on DQ7 bit and
DQ6 never stops toggling. Once the device has exceeded timing limits, the DQ5 bit will
indicate a “1”. Please note that this is not a device failure condition since the device was
incorrectly used. If this occurs, reset the device.
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PDF描述 |
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| PSD4235G2(中文) | Flash In-System-Programmable Peripherals for 16-Bit MCUs(用于16位MCU的閃速在系統(tǒng)可編程外圍芯片) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4-16 | 制造商:Tamura Corporation of America 功能描述: |
| PSD4-20 | 制造商:MICROTRAN 功能描述:POWER TRANSFORMER, 6 VA |
| PSD4235G2-70U | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 4M 70ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD4235G2-90U | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4235G2-90UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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