參數(shù)資料
型號： PSD501B1-C-90JI
廠商： 意法半導(dǎo)體
英文描述： Low Cost Field Programmable Microcontroller Peripherals
中文描述： 低成本現(xiàn)場可編程微控制器外圍設(shè)備
文件頁數(shù)： 46/153頁
文件大?。?/td> 1036K
代理商： PSD501B1-C-90JI
PSD5XX Famly
43
Control Register
This register is used in both Standard MCU I/O Mode and Address Out modes. For setting
a Standard MCU I/O Mode, a “1” must be written to the corresponding bit in the register.
Writing a “0” to the register is required for the Address Out mode. The register has a default
value of “0” after reset.
Drection Register
This register is used to control the direction of data flow in the I/O ports. Writing a “1” to
the corresponding bit in the register configures the port to be an output port, and a “0”
forces the port to be an input port. The I/O configuration of the port pins can be determined
by reading the Direction Register. After reset, the pins are in input mode.
Open Drain Register
This register determines whether the output pin driver of Port C or D is a CMOS driver or
an Open Drain driver. Writing a “0” to the register selects a CMOS driver, while a “1” selects
an Open Drain driver.
Special Function Register
Writing a “1” bit to this register sets up the corresponding pin to operate in Special Function
Out mode.
PLD– I/ORegister
This is a read only status register. Reading a "1" indicates the corresponding pin is
configured as a PLD pin. A "0" indicates the pin is an I/O pin.
Data In Register
This register is used in the Standard MCU I/O Mode configuration to read the input pins.
Data Out Register
This register holds the output data in the Standard MCU I/O Mode. The contents of the
register can also be read.
Macrocell Out Register
This register enables the user to read the outputs of the GPLD macrocell (PA, PB, and PE
macrocells).
I/ORegister Address Ofset
The I/O Register can be accessed by the microcontroller during normal read/write bus
cycles. The address of a register is defined as:
CSIOP + register address offset
The CSIOP is the base address that is defined in the ABEL file and occupies a 256 byte
space. The register address offset lies within this 256 byte space. Tables 15 and 15a are
the address offset of the registers.
I/OPorts
(Cont.)
相關(guān)PDF資料
PDF描述
PSD511B1-C-90JI Low Cost Field Programmable Microcontroller Peripherals
PSD501B1-C-90UI EXPRESS ETHERNET SWITCH 16 PORT
PSD511B1-C-90UI Low Cost Field Programmable Microcontroller Peripherals
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PSD502B1-C-15J Low Cost Field Programmable Microcontroller Peripherals
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD501B1C-90JI 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 256K 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD501B1-C-90UI 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals
PSD501H 制造商:PACELEADER 制造商全稱:PACELEADER INDUSTRIAL 功能描述:SURFACE MOUNT SCHOTTKY BARRIER DIODES
PSD502B1 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PSD5XX/ZPSD5XX FAMILY FIELD-PROGRAMMABLE MICROCONTROLLER PERIPHERALS
PSD502B1-12J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
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