參數(shù)資料
型號： PSD501B1-C-90JI
廠商： 意法半導(dǎo)體
英文描述： Low Cost Field Programmable Microcontroller Peripherals
中文描述： 低成本現(xiàn)場可編程微控制器外圍設(shè)備
文件頁數(shù)： 55/153頁
文件大?。?/td> 1036K
代理商： PSD501B1-C-90JI
PSD5XX Famly
52
The PSD5XX provides EPROM memory for code storage and SRAM memory for scratch
pad usage. Chip selects for the memory blocks come from the DPLD decoding logic and are
defined by the user in the PSDsoft Software. Figure 26 shows the organization of the
Memory Block.
All PSD families use Zero-power memory techniques that place memory into standby
between MCU accesses. The memory becomes active briefly after an address transition,
then delivers new data to the outputs, latches the outputs, and returns to standby. This is
done automatically and the designer has to do nothing special to benefit from this feature.
9.4.1 EPROM
The PSD5XX provides three EPROM densities: 256Kbit, 512Kbit or 1Mbit. The EPROM
is divided into four 8K, 16K or 32K byte blocks. Each block has its own chip select signals
(ES0 – ES3). The EPROM can be configured as 32K x 8, 64K x 8 or 128K x 8 for
microcontrollers with an 8-bit data bus. For 16-bit data buses, the EPROM is configured as
16K x 16, 32K x 16, or 64K x 16.
9.4.2 SRAM
The SRAM has 16Kbits of memory, organized as 2K x 8 or 1K x 16. The SRAM is enabled
by the chip select signal RS0 from the DPLD. The SRAM has a battery back-up (STBY)
mode. This back-up mode is invoked when the V
CC
voltage drops under the VSTBY voltage
by 0.6 V. The VSTBY voltage is connected only to the SRAM and cannot be lower than
2.7 volts. The SRAM Data Retention voltage is 2 volts.
9.4.3 Memory Select Map
The EPROM and SRAM chip select equations are defined in the ABEL file in terms of
address and other DPLD inputs. The memory space for the EPROM chip select
(ES0 – ES3) should not be larger than the EPROM block (8KB, 16KB or 32KB) it is
selecting.
The following rules govern how the internal PSD5XX memory selects/space are defined:
J
The EPROM blocks address space cannot overlap
J
SRAM, internal I/O and Peripheral I/O space cannot overlap
J
SRAM, internal I/O and Peripheral I/O space can overlap EPROM space, with priority
given to SRAM or I/O. The portion of EPROM which is overlapped cannot be accessed.
The Peripheral I/O space refers to memory space occupied by peripherals when Port A is
configured in the Peripheral I/O Mode.
9.4
Memory
Block
相關(guān)PDF資料
PDF描述
PSD511B1-C-90JI Low Cost Field Programmable Microcontroller Peripherals
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PSD511B1-C-90UI Low Cost Field Programmable Microcontroller Peripherals
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD501B1C-90JI 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 256K 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD501B1-C-90UI 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Low Cost Field Programmable Microcontroller Peripherals
PSD501H 制造商:PACELEADER 制造商全稱:PACELEADER INDUSTRIAL 功能描述:SURFACE MOUNT SCHOTTKY BARRIER DIODES
PSD502B1 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PSD5XX/ZPSD5XX FAMILY FIELD-PROGRAMMABLE MICROCONTROLLER PERIPHERALS
PSD502B1-12J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
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