參數(shù)資料
型號： PSD501B1
英文描述： PSD5XX/ZPSD5XX FAMILY FIELD-PROGRAMMABLE MICROCONTROLLER PERIPHERALS
中文描述： PSD5XX/ZPSD5XX家庭領域，可編程微控制器外設
文件頁數(shù)： 64/153頁
文件大?。?/td> 1036K
代理商： PSD501B1
PSD5XX Famly
61
Power
Management
Unit
(Cont.)
9.5.4 Oher Power Saving Options
The PSD5XX provides additional power saving options. These options, except the SRAM
Standby Mode, can be enabled/disabled by setting up the corresponding bit in the PMMR.
J
EPROM
The EPROM power consumption in the PSD is controlled by bit 3 in the
PMMR0 – EPROM CMiser. Upon reset the CMiser bit is OFF. This will cause the
EPROM to be ON at all times as long as CSI is enabled (low). The reason this mode is
provided is to reduce the access time of the EPROM by 10 ns relative to the low power
condition when CMiser is ON. If CSI is disabled (high) the EPROM will be deselected
and will enter standby mode (OFF) overriding the state of the CMiser.
If CMiser is set (ON) then the EPROM will enter the standby mode when not selected.
This condition can take place when CSI is high or when CSI is low and the EPROM is
not accessed. For example, if the MCU is accessing the SRAM, the EPROM will be
deselected and will be in low power mode.
An additional advantage of the CMiser is achieved when the PSD is configured in the
by 8 mode (8 bit data bus). In this case an additional power savings is achieved in the
EPROM (and also in the SRAM) by turning off 1/2 of the array even when the EPROM
is accessed (the array is divided internally into odd and even arrays).
The power consumption for the different EPROM modes is given in the DC
Characteristics table under I
CC
(DC) EPROM Adder.
J
SRAM Standby Mode
The SRAM has a dedicated supply voltage V
STBY
that can be used to connect a
battery. When V
CC
becomes lower than V
STBY
–0.6 then the PSD will automatically
connect the V
STBY
as a power source to the SRAM. The SRAM Standby Current (I
STBY
)
is typically 0.5 μA.
SRAM data retention voltage V
DF
is 2 V minimum.
J
Zero Power ZPLD
ZPLD power/speed is controlled by the ZPLD_Turbo bit (bit 4) in the PMMR0. After
reset the ZPLD is in Turbo mode and runs at full power and speed. By setting the bit to
“1”, the Turbo mode is disabled and the ZPLD is consuming Zero Power current if the
inputs are not switching for an extended time of 100 ns. The propagation delay time will
be increased by 10ns after the Turbo bitis set to “1” (turned off) if the inputs change at a
frequency of less than 15 MHz.
相關PDF資料
PDF描述
PSD502B1 60V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a TO-254AA package; Similar to IRHMB57064 with optional Total Dose Rating of 1000kRads
PSD511B1 PSD5XX/ZPSD5XX FAMILY FIELD-PROGRAMMABLE MICROCONTROLLER PERIPHERALS
PSD512B0 500V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a TO-205AF package; A IRHF7430SE with Standard Packaging
PSD512B1 -100V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a SMD-2 package; Similar to IRHNA597160 with optional Total Dose Rating of 300kRads
PSD511B1-C-70U Low Cost Field Programmable Microcontroller Peripherals
相關代理商/技術參數(shù)
參數(shù)描述
PSD501B1-12J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD501B1-12JI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD501B1-12LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD501B1-12U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD501B1-12UI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
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