參數(shù)資料
型號(hào)： PSD511B1
英文描述： Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入)
中文描述： 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備（可編程邏輯，16K的位的SRAM，40余個(gè)可編程輸入/輸出，通用PLD的有61個(gè)輸入）
文件頁(yè)數(shù)： 106/130頁(yè)
文件大小： 704K
代理商： PSD511B1
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PSD5XX Famly
6-106
Reset Input
The reset input to the PSD5XX (RESET) is an active low signal which resets some of
the internal devices and configuration registers. The Timing Diagram in the AC/DC
characterization section shows the reset signal timing requirement. The active low range has
a minimum T1 duration. After the rising edge of RESET, the PSD5XX remains in
reset during T2 range. (See Figure 59). The PSD5XX must be reset at power up before it
can be used.
ZPLDand Memory During Reset
While the Reset Input is active, the ZPLD generates outputs as defined in the PSDabel
equations. The EPROM and SRAM blocks respond to the microcontroller bus cycle during
reset, but the data is not guaranteed.
Register Values During and After Reset
Table 34 summarizes the status of the volatile register values during and after reset. The
default values of the volatile registers are “0” after reset.
ZPLDMacrocell Initialization
The D flip flops in the macrocells in the GPLD can be cleared by:
J
A product term (.RE) defined by the user, in PSDabel or
J
The MACRO-RST (Reset) input, enabled and defined in PSDabel.
The Timer and Interrupt Controller macrocells in the PPLD are always cleared by the
Reset input.
Register Name
Control
Data Out (data or address)
Direction
Open Drain
Page Register
PMMR0, PMMR1
VM
DLCY
CMD0 – CMD3
Status Flags
Global Command
Device
Reset State
Port A, B, C, D, E
Port A, B, C, D, E
Port A, B, C, D, E
Port C, D
Page Logic
Power Management Unit
Volatile Memory
Timer
Timer
Timer
Timer
Set to “0” (Address Out Mode)
Set to “0”
Set to “0” – Input Mode
Set to “0” – CMOS Outputs
Set to “0”
Set to “0”
Set to “0”
Set to “0”
Set to “0”, Clear
Set to “0”, Clear
Set to “0”, Clear
IMG0 – IMG3,
CNTR0 – CNTR3
Timer
Undefined
Interrupt
Interrupt Controller
Set to “0”, Disabled
System
Configuration
(Cont.)
Table 34. Registers Reset Values
Port Configuration
Port I/O
ZPLD Output
Address Out
Data Port
Reset
Input
Active
Tri-stated
Tri-stated
Standby Mode
Unchanged
Depend on Inputs to the ZPLD
Not Defined
Tri-stated
Depending on Status of
Clock Input to the Counter/Timer
Tri-state
Special Function Out
Tri-stated
Peripheral I/O
Tri-stated
Table 35. I/OPin Status During Reset and Standby Mode
相關(guān)PDF資料
PDF描述
PSD502B1 Field Programmable Microcontroller Peripherals(可編程邏輯，16K位SRAM,40個(gè)可編程I/O,通用PLD有61個(gè)輸入)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD511B1-12J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD511B1-12JI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD511B1-12LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD511B1-12U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD511B1-12UI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
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