參數(shù)資料
型號: PSD512B1
英文描述: -100V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a SMD-2 package; Similar to IRHNA597160 with optional Total Dose Rating of 300kRads
中文描述: PSD5XX/ZPSD5XX家庭領(lǐng)域,可編程微控制器外設(shè)
文件頁數(shù): 151/153頁
文件大小: 1036K
代理商: PSD512B1
PSD5XX Famly
148
21.0
Process
Change Notice,
October 1, 1998
PSD5XX Functional Change:
A change has been implemented in the most recent silicon that improves the way that the
Image Register is updated. This change only applies to Event Count Mode for counter units
CTU0, CTU1, and CTU3.
Previous PSD5XX Silicon:
The Image Register was not updated with the actual event count upon exiting Freeze
mode. As a result, in certain circumstances, the Image Register may not have reflected the
actual event count. Although an incorrect count may have been read from the Image
Register at a given time, no event counts were ever lost because the microcontroller would
eventually read the correct value in the Image Register on subsequent freeze and read
cycles.
Current PSD5XX Silicon:
The Image register is now automatically updated with the actual count upon exiting the
Freeze mode. This ensures that on the very next freeze and read cycle, the microcontroller
will read the actual count from the Image register. There are two restrictions however:
1. If an event occurs within one timer clock period plus two CLKIN periods after the image
register is unfrozen, then the Image Register will not reflect that event on the very next
freeze and read cycle (timer clock period is defined on page 6-79 of the 1996 PSD data
book). Instead, the event will appear in the Image Register on the subsequent freeze
and read cycle.
2. The time between an unfreeze and the beginning of the next freeze has the same time
constraint as number one. There must be at least one timer clock period plus two CLKIN
periods between the end of one freeze cycle and the beginning of the next. This timing
can be controlled by software design.
To reduce the chance of getting a delayed count in the Image Register due to restriction
number 1, execute a software Load/Store command just prior to freezing and reading the
Image Register to force an update to the Image count.
Backwards Compatibility:
This improvement should have no impact on current designs unless these designs
were compensating for lost events. In such cases, compatibility is dependent on the
compensation method that was used. Please contact WSI at apphelp@wsiusa.com if you
think you have an issue or have any questions.
相關(guān)PDF資料
PDF描述
PSD511B1-C-70U Low Cost Field Programmable Microcontroller Peripherals
PSD501B1-C-90JI Low Cost Field Programmable Microcontroller Peripherals
PSD511B1-C-90JI Low Cost Field Programmable Microcontroller Peripherals
PSD501B1-C-90UI EXPRESS ETHERNET SWITCH 16 PORT
PSD511B1-C-90UI Low Cost Field Programmable Microcontroller Peripherals
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD512B1-12J 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD512B1-12JI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD512B1-12LI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD512B1-12U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral
PSD512B1-12UI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Peripheral