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參數(shù)資料
| 型號： | PSD813F1-A-90JI |
| 廠商： | 意法半導體 |
| 英文描述： | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| 中文描述： | Flash在系統(tǒng)可編程ISP的外設的8位微控制器 |
| 文件頁數(shù)： | 54/110頁 |
| 文件大?。?/td> | 1685K |
| 代理商： | PSD813F1-A-90JI |
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PSD813F1
54/110
MCU I/O Mode
In the MCU I/O Mode, the microcontroller uses the
PSD ports to expand its own I/O ports. By setting
up the CSIOP space, the ports on the PSD are
mapped into the microcontroller address space.
The addresses of the ports are listed in
Table
6., page 17
.
A port pin can be put into MCU I/O mode by writing
a
‘
0
’
to the corresponding bit in the Control Regis-
ter. The MCU I/O direction may be changed by
writing to the corresponding bit in the Direction
Register, or by the output enable product term.
See
the
section
entitled
Mode, page 56
. When the pin is configured as an
output, the content of the Data Out Register drives
the pin. When configured as an input, the micro-
controller can read the port input through the Data
In buffer. See
Figure 27., page 53
.
Ports C and D do not have Control Registers, and
are in MCU I/O mode by default. They can be used
for PLD I/O if equation are written for them in PS-
Dabel.
PLD I/O Mode
The PLD I/O Mode uses a port as an input to the
CPLD
’
s Input Macrocells, and/or as an output from
the CPLD
’
s Output Macrocells. The output can be
tri-stated with a control signal. This output enable
control signal can be defined by a product term
Peripheral
I/O
from the PLD, or by setting the corresponding bit
in the Direction Register to
‘
0.
’
The corresponding
bit in the Direction Register must not be set to
‘
1
’
if
the pin is defined as a PLD input pin in PSDabel.
The PLD I/O Mode is specified in PSDabel by de-
claring the port pins, and then writing an equation
assigning the PLD I/O to a port.
Address Out Mode
For microcontrollers with a multiplexed address/
data bus, Address Out Mode can be used to drive
latched addresses onto the port pins. These port
pins can, in turn, drive external devices. Either the
output enable or the corresponding bits of both the
Direction Register and Control Register must be
set to a
‘
1
’
for pins to use Address Out Mode. This
must be done by the MCU at run-time. See
Table
21., page 55
for the address output pin assign-
ments on Ports A and B for various MCUs.
For non-multiplexed 8-bit bus mode, address lines
A7-A0 are available to Port B in Address Out
Mode.
Note:
do not drive address lines with Address Out
Mode to an external memory device if it is intended
for the MCU to boot from the external device. The
MCU must first boot from PSD memory so the Di-
rection and Control register bits can be set.
Table 19. Port Operating Modes
Note: 1. Can be multiplexed with other I/O functions.
Port Mode
Port A
Port B
Port C
Port D
MCU I/O
Yes
Yes
Yes
Yes
PLD I/O
McellAB Outputs
McellBC Outputs
Additional Ext. CS Outputs
PLD Inputs
Yes
No
No
Yes
Yes
Yes
No
Yes
No
Yes
No
Yes
No
No
Yes
Yes
Address Out
Yes (A7-A0
Yes (A7-A0)
or (A15-A8)
No
No
Address In
Yes
Yes
Yes
Yes
Data Port
Yes (D7-D0)
No
No
No
Peripheral I/O
Yes
No
No
No
JTAG ISP
No
No
Yes
1
No
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PSD813F1A-90JI | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD813F1A-90JT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V |
| PSD813F1-A-90M | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD813F1A-90M | 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD813F1-A-90MI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
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