參數(shù)資料
型號： PSD813F1-A
廠商： 意法半導(dǎo)體
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： Enhanced High Power Factor Preregulator 16-PDIP 0 to 70
中文描述： Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁數(shù)： 93/110頁
文件大小： 1685K
代理商： PSD813F1-A
93/110
PSD813F1
Table 58. WRITE Timing (3V devices)
Note: 1. Any input used to select an internal PSD function.
2. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
3. WR has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active WRITE signal.
5. Assuming WRITE is active before data becomes valid.
6. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
Table 59. Flash Program, WRITE and Erase Times (5V devices)
Symbol
Parameter
Note: 1. Programmed to all zero before erase.
2. The polling status, DQ7, is valid t
Q7VQV
time units before the data byte, DQ0-DQ7, is valid for reading.
Symbol
Parameter
Conditions
-15
-20
Unit
Min
Max
Min
Max
t
LVLX
ALE or AS Pulse Width
26
30
t
AVLX
Address Setup Time
(Note
1
)
10
12
ns
t
LXAX
Address Hold Time
(Note
1
)
12
14
ns
t
AVWL
Address Valid to Leading
Edge of WR
(Notes
1,3
)
20
25
ns
t
SLWL
CS Valid to Leading Edge of WR
(Note
3
)
20
25
ns
t
DVWH
WR Data Setup Time
(Note
3
)
45
50
ns
t
WHDX
WR Data Hold Time
(Note
3
)
8
10
ns
t
WLWH
WR Pulse Width
(Note
3
)
48
53
ns
t
WHAX1
Trailing Edge of WR to Address Invalid
(Note
3
)
12
17
ns
t
WHAX2
Trailing Edge of WR to DPLD Address Invalid
(Note
3,6
)
0
0
ns
t
WHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
(Note
3
)
45
50
ns
t
DVMV
Data Valid to Port Output Valid
Using Macrocell Register Preset/Clear
(Notes
3,5
)
90
100
ns
t
AVPV
Address Input Valid to Address
Output Delay
(Note
2
)
48
55
ns
t
WLMV
WR Valid to Port Output Valid Using
Macrocell Register Preset/Clear
(Notes
3,4
)
90
100
ns
Min.
Typ.
Max.
Unit
Flash Program
8.5
s
Flash Bulk Erase
1
(pre-programmed)
3
30
s
Flash Bulk Erase (not pre-programmed)
10
s
t
WHQV3
Sector Erase (pre-programmed)
1
30
s
t
WHQV2
Sector Erase (not pre-programmed)
2.2
s
t
WHQV1
Byte Program
14
1200
μs
Program / Erase Cycles (per Sector)
100,000
cycles
t
WHWLO
Sector Erase Time-Out
100
μs
t
Q7VQV
DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)
2
30
ns
相關(guān)PDF資料
PDF描述
PSD813F1-A-12JI Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD813F1-A-12MI Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD813F1-A-90J Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD813F1-A-90JI Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD813F1A-90MI Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD813F1A-12J 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD813F1-A-12JI 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD813F1A-12JI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD813F1A-12JT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD813F1A-12M 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*